Description: 秒表可计时，用VHDL编译的源代码，从0.1到60秒计时，解压后直接用Quartus打开project即可-Stopwatch timer can be used to compile the VHDL source code, from 0.1 to 60 seconds from time, after extracting the direct use of Quartus can open the project Platform: |
Size: 577536 |
Author:xie |
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Description: AHDL parametrized timer - for Altera Quartus compiler only-AHDL parametrized timer- for Altera Quartus compiler only Platform: |
Size: 1024 |
Author:kkris |
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Description: Quartus II was a development tool of CPLD / FPGA by Altera Company. Quartus II provides a fully integrated circuit structure and has nothing with the development package environment, it has all the features of digital logic design, it is including: available schematic, block diagram, VerilogHDL, AHDL and VHDL complete circuit description which save it as a design entity documents, chip (circuit) connection layout editor, LogicLock design method, the user can create and optimize the system, and then add the original system which is smaller or no effect on the performance of the follow-up module, powerful logic synthesis tool, complete The logic circuit functional simulation and timing simulation tools, Timer / Time Series Analysis and critical path analysis which can use SignalTap II embedded logic analysis tool for logical analysis-Quartus II was a development tool of CPLD/FPGA by Altera Company. Quartus II provides a fully integrated circuit structure and has nothing with the development package environment, it has all the features of digital logic design, it is including: available schematic, block diagram, VerilogHDL, AHDL and VHDL complete circuit description which save it as a design entity documents, chip (circuit) connection layout editor, LogicLock design method, the user can create and optimize the system, and then add the original system which is smaller or no effect on the performance of the follow-up module, powerful logic synthesis tool, complete The logic circuit functional simulation and timing simulation tools, Timer/Time Series Analysis and critical path analysis which can use SignalTap II embedded logic analysis tool for logical analysis Platform: |
Size: 202752 |
Author:jay |
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Description: 本设计选用 ALTERA 公司的 EP1C12Q240C8 芯片，利用 VHDL 语言采用自
顶向下的方法在 Quartus Ⅱ环境下完成了数字钟的设计，最后在实验箱上进行测
试。该数字钟包含的功能有计时、显示星期、校时校分、清零、整点报时、音乐
闹铃。-The design uses the silicon chip EP1C12Q240C8 produced by the company of
ALTERA. And with the help of VHDL, the design of a digital clock is completed
using the top-down approach under Quartus Ⅱ, finally carried out in the SmartSOPC.
Functions of the digital clock are: timer, showing day, setting time, resetting, Chime
on every hour, and alarm with music. Platform: |
Size: 231424 |
Author:费孝海 |
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