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[Other resource] USB接口控制器参考设计_xilinx提供_vhdl

Description: USB接口控制器参考设计，xilinx提供的VHDL源代码-USB interface controller reference design for Xilinx VHDL source code
Platform: | Size: 461172 | Author: 陈旭 | Hits:

[VHDL-FPGA-Verilog] USB接口控制器参考设计_xilinx提供_vhdl

Description: USB接口控制器参考设计，xilinx提供的VHDL源代码-USB interface controller reference design for Xilinx VHDL source code
Platform: | Size: 460800 | Author: 陈旭 | Hits:

[VHDL-FPGA-Verilog] USB_VHDL_CODE

Description: USB接口控制器参考设计VHDL代码,方便开发FPGA人员进行USB的开发，是一个不错的源码。-USB interface controller reference design VHDL code, facilitate the development of FPGA personnel USB development, is a good source.
Platform: | Size: 60416 | Author: hyl | Hits:

[VHDL-FPGA-Verilog] Chapter6Sample

Description: 描述了使用FPGA接口PDIUSBD12开发USB接口的流程.-Describes the use of FPGA Interface USB interface PDIUSBD12 development flow.
Platform: | Size: 141312 | Author: 玄冰 | Hits:

[Other] ALTERA-USB-BLASTER

Description: ALTERA-USB-BLASTER is a pdf file which is dawed by protel.
Platform: | Size: 18432 | Author: hewen1983 | Hits:

[USB develop] ISP1581veriloghdl

Description: usb 接口芯片isp1581 程序，调试过了，好使的-usb interface chip isp1581 procedures, after debugging, so that the
Platform: | Size: 626688 | Author: cj | Hits:

[USB develop] usb

Description: 实现了USB接口。介绍了如何使用VERILOG语言实现USB的程序设计。-Realize the USB interface. Introduce how to use the Verilog language programming USB realize.
Platform: | Size: 140288 | Author: xiexiao | Hits:

[VHDL-FPGA-Verilog] la_usb-SPISRAM

Description: 有关到SRAM的VHDL程序,也涉及到USB接口，希望对大家有所帮助-Related to the SRAM of the VHDL process involves the USB interface, and they hope to help everyone
Platform: | Size: 2048 | Author: 李锐 | Hits:

[USB develop] USB

Description: fpga设计的usb接口源程序，欢迎指导-FPGA design usb interface source code, welcomed the guidance of
Platform: | Size: 140288 | Author: 陈楠 | Hits:

[USB develop] usb_phy

Description: usb接口协议。It was tested with a USB 1.1 core I have written on a XESS XCV800 board with a a Philips PDIUSBP11A transceiver. -usb interface protocol. It was tested with a USB 1.1 core I have written ona XESS XCV800 board with aa Philips PDIUSBP11A transceiver.
Platform: | Size: 11264 | Author: 颜新卉 | Hits:

[VHDL-FPGA-Verilog] 21

Description: 是FPGA程序。题目是USB接口应用系统设计实例-Is the FPGA program. USB interface application entitled System Design Examples
Platform: | Size: 10240 | Author: 王洪亮 | Hits:

[VHDL-FPGA-Verilog] usb_phy.tar

Description: Very simple USB 1.1 PHY. Includes all the goodies: serial/parallel conversion, bit stuffing/unstuffing, NRZI encoding decoding. Uses a simplified UTMI interface. Currently doesn t do any error checking in the RX section [should probably check for bit unstuffing errors]. Otherwise complete and fully functional. There is currently no test bench available. This core is very simple and is proven in hardware. I see no point of writing a test bench at this time.
Platform: | Size: 7168 | Author: eldis | Hits:

[VHDL-FPGA-Verilog] usb_FPGA

Description: 实现USB接口功能的VHDL和verilog完整源代码-Implementation USB interface functions of the VHDL and Verilog source code integrity
Platform: | Size: 260096 | Author: liang | Hits:

[VHDL-FPGA-Verilog] USB

Description: USB通信协议的硬件描述语言代码，用于FPGA的总线接口控制器开发-USB communication protocol of the hardware description language code for the FPGA bus interface controller development
Platform: | Size: 140288 | Author: shigengxin | Hits:

[USB develop] usb

Description: USBHostSlave is a USB 1.1 host and Device IP core. – Supports full speed (12Mbps) and low speed (1.5Mbps) operation. – USB Device has four endpoints, each with their own independent FIFO. – Supports the four types of USB data transfer control, bulk, interrupt, and isochronous transfers. – Host can automatically generate SOF packets. – 8-bit Wishbone slave bus interface. – FIFO depth configurable via paramters.-USBHostSlave is a USB 1.1 host and Device IP core. – Supports full speed (12Mbps) and low speed (1.5Mbps) operation. – USB Device has four endpoints, each with their own independent FIFO. – Supports the four types of USB data transfer control, bulk, interrupt, and isochronous transfers. – Host can automatically generate SOF packets. – 8-bit Wishbone slave bus interface. – FIFO depth configurable via paramters.
Platform: | Size: 6144 | Author: polito | Hits:

[VHDL-FPGA-Verilog] DE2_demonstrations

Description: DE2开发板上的资料,主要是他的例子,含有各种接口程序,如VGA,USB,LCD等-DE2 development board information, mainly his example, contain a variety of interface program, such as VGA, USB, LCD, etc.
Platform: | Size: 44079104 | Author: 翁文天 | Hits:

[VHDL-FPGA-Verilog] usbip

Description: USB接口控制器参考设计，xilinx提供VHDL代码 -USB interface controller reference design, xilinx provide VHDL code
Platform: | Size: 198656 | Author: 李丽 | Hits:

[VHDL-FPGA-Verilog] cp_uart_6

Description: 用CPLD驱动UART转USB芯片CP2102的verilog代码，与PC通信 包括CP2102的配置 驱动等-Using CPLD to drive the USB-UART CP2102 interface. verilog code, then communicate with PC, including the configuration and drivers, etc.
Platform: | Size: 1024 | Author: vicky | Hits:

[USB develop] usb_funct

Description: USB接口开发的源代码,包括软件和硬件，学习USB非常好用的资料-USB interface, the development of source code, including software and hardware, learning is very easy to use USB data
Platform: | Size: 196608 | Author: hao3361 | Hits:

[VHDL-FPGA-Verilog] USB

Description: 用VHDL编写实现的USB接口控制器源码，自带testbench，解压后用ISE打开工程文件即可。-Prepared with the VHDL source code to achieve the USB interface controller, bring their own testbench, after decompression project file can be opened with the ISE.
Platform: | Size: 156672 | Author: 陈阳 | Hits:
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