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Description: 原理图常见错误： （1）ERC报告管脚没有接入信号： a. 创建封装时给管脚定义了I/O属性； b.创建元件或放置元件时修改了不一致的grid属性，管脚与线没有连上； c. 创建元件时pin方向反向，必须非pin name端连线。 （2）元件跑到图纸界外：没有在元件库图表纸中心创建元件。 （3）创建的工程文件网络表只能部分调入pcb：生成netlist时没有选择为global。 （4）当使用自己创建的多部分组成的元件时，千万不要使用annotate.-principle of common mistakes : (1) ERC report no access to signal pins : a. creation package to the pin at the definition of I / O attribute; b. create components or modify components placed inconsistent grid attributes, and the lines do not pin connection; c. create components reverse direction when the pin, non-name-pin connections. (2) components went to the drawings profession : no paper charts component library center components. (3) the creation of the document network table works only partially transferred PCB : netlist generation did not choose to global. (4) When the use of their own creation, multi-component element, we must use annotate.
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Size: 25051 |
Author: 李越 |
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Description: 这是一个根据网表建立矩阵的程序，这些矩阵可以用来解方程-This is a netlist based on the procedures established matrix, which can be used for matrix equation solution
Platform: |
Size: 16054 |
Author: 胡云 |
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Description: This paper presents a low-power asynchronous implementation of the 80C51 microcontroller. It was realized in a 0.5 µ m CMOS process and it shows a power advantage of a factor 4 compared to a recent synchronous implementation in the same technology. The chip is fully bit compatible with the synchronous implementation, and timing compatible for external memory access. The circuit is a compiled VLSI-program, using Tangram as VLSI-programming language and the Tangram tool set to compile the design automatically to a standard-cell netlist. This design approach proves to be powerful enough to describe the microcontroller and derive an efficient implementation. Further, it offers the designer the possibility to explore various alternatives in the design space.
Platform: |
Size: 98828 |
Author: 啊灿 |
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Description: iic总线控制器VHDL实现
-- VHDL Source Files:
i2c.vhd -- top level file
i2c_control.vhd -- control function for the I2C master/slave
shift.vhd -- shift register
uc_interface.vhd -- uC interface function for an 8-bit 68000-like uC
upcnt4.vhd -- 4-bit up counter
i2c_timesim.vhd -- post-route I2C simulation netlist
Platform: |
Size: 889991 |
Author: benny |
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Description: 目 錄 1
目 錄
Unix基本指令 第一章
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1.1 本章教學大綱...................................................1-2
1.2 Unix的歷史......................................................1-2
1.3 Unix基本指令簡介..........................................1-5
1.4 編輯器vi.........................................................1-45
1.5 Unix的基本檔案系統.....................................1-51
1.6 相關網站.........................................................1-60
1.7 課後習題相關網站.........................................1-61
CMOS VLSI設計概念與Design Flow 第二章
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2.1 本章教學大綱...................................................2-2
2.2 IC的各種設計方法..........................................2-2
2.3 MOS電晶體....................................................2-10
2.4 CMOS的技術.................................................2-16
2.5 Bottom Up與Top Down設計........................2-25
2.6 Full Custom IC的設計流程............................2-29
2.7 Design Frame work II之檔案結構..................2-33
2.8 CAD/CAE軟體的資料格式標準....................2-40
2.9 國科會晶片實現中心 ( CIC )........................2-42
2.10 作業.................................................................2-44
2 目 錄
第
如何進入Cadence 三章
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3.1 如何進入Cadence.............................................3-2
3.2 如何將Cadence 4.3.X的Lib轉成OPUS-97A 4.4版的Lib......................................................3-4
3.3 建立新的Library............................................3-12
3.4 建立新的cellview...........................................3-17
Schematic 第四章
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4.1 Schematic 指令介紹.......................................4-2
4.2 Schematic繪圖視窗選項介紹..........................4-3
4.3 實作範例：建立一Buffer的Schematic View4-27
4.4 將Schematic View轉出網路檔 (netlist) 的CDL out...................................................................4-30
Symbol 第五章
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5.1 Symbol View快速選擇介紹.............................5-2
5.2 Symbol繪圖視窗選擇項介紹...........................5-4
5.3 實作範例：建立一Buffer的Symbol View...5-22
Layout 第六章
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6.1 Layout View......................................................6-2
6.2 Layer Selection Window (LSW) 視窗..............6-3
6.3 Layout快速選項列介紹...................................6-3
6.4 Layout View繪圖視窗選擇項介紹..................6-6
6.5 實作範例：建立一Buffer的Layout View....6-37
目 錄 3
第
Dracula 七章
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7.1 Dracula介紹.....................................................7-2
7.2 DRC(Design Rule Checking).............................7-2
7.3 DRC錯誤範例說明........................................7-15
7.4 DRC Error Message.........................................7-24
7.5 ERC錯誤範例說明.........................................7-27
7.6 LVS(Layout vs. Schematic Check)..................7-32
7.7 LVS錯誤範例說明.........................................7-49
7.8 LVS的錯誤型態.............................................7-62
7.9 LPE(Layout Parameter Extraction)..................7-78
I/O Circuit及Package 第八章
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8.1 I/O Circuit概述.................................................8-2
8.2 基本分類...........................................................8-4
8.3 CIC之I/O PAD................................................8-9
8.4 I/O PAD的規劃..............................................8-28
8.5 範 例.............................................................8-34
8.6 包裝 (Package)...............................................8-36
SPICE Simulation 第九章
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9.1 本章教學大綱...................................................9-2
9.2 SPICE Simulation的基本概念..........................9-2
9.3 SPICE的語法...................................................9-5
9.4 用HSPICE來模擬............................................9-8
9.5 用PSPICE來模擬..........................................9-53
9.6 用IsSPICE來模擬..........................................9-58
9.7 用SBTSPICE來模擬.....................................9-68
4 目 錄
第
Design Guide 十章
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10.1 本章教學大綱.................................................10-2
10.2 Design for Reliability......................................10-2
10.3 Design for Testability....................................10-27
範例：JK FF 第十一章
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11.1 本章教學大綱.................................................11-2
11.2 JK正反器電路圖............................................11-2
11.3 建立所有的邏輯閘.........................................11-3
11.4 JK正反器之schematic及symbol view........11-10
11.5 用HSPICE來模擬JK正反器之狀態輸出...11-11
11.6 Debug............................................................11-16
11.7 PDRACULA的驗證.....................................11-29
教育性晶片製作申請程序及範例 附錄一
Design Rules實例 (Mead & Conway) 附錄二
XV使用說明 附錄三
將電路加入IOPAD的方法 附錄四
加入IOPAD的幾個動作 附錄五
積體電路電路布局保護法 附錄六
參考資料
Platform: |
Size: 9318659 |
Author: g9676612@cycu.edu.tw |
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Description: 这是一个根据网表建立矩阵的程序，这些矩阵可以用来解方程-This is a netlist based on the procedures established matrix, which can be used for matrix equation solution
Platform: |
Size: 223232 |
Author: 胡云 |
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Description: This paper presents a low-power asynchronous implementation of the 80C51 microcontroller. It was realized in a 0.5 µ m CMOS process and it shows a power advantage of a factor 4 compared to a recent synchronous implementation in the same technology. The chip is fully bit compatible with the synchronous implementation, and timing compatible for external memory access. The circuit is a compiled VLSI-program, using Tangram as VLSI-programming language and the Tangram tool set to compile the design automatically to a standard-cell netlist. This design approach proves to be powerful enough to describe the microcontroller and derive an efficient implementation. Further, it offers the designer the possibility to explore various alternatives in the design space.
Platform: |
Size: 98304 |
Author: 啊灿 |
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Description: 这是一本怎样去写hspice 网表的一个reference 特别是新手开始写 hspice 其实写熟了 会很快
Platform: |
Size: 562176 |
Author: zhujia |
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Description: iic总线控制器VHDL实现
-- VHDL Source Files:
i2c.vhd -- top level file
i2c_control.vhd -- control function for the I2C master/slave
shift.vhd -- shift register
uc_interface.vhd -- uC interface function for an 8-bit 68000-like uC
upcnt4.vhd -- 4-bit up counter
i2c_timesim.vhd -- post-route I2C simulation netlist
-IIC bus controller VHDL realize- VHDL Source Files: i2c.vhd- top level file i2c_control.vhd- control function for the I2C master/slave shift.vhd- shift register uc_interface.vhd- uC interface function for an 8-bit 68000-like uC upcnt4.vhd- 4-bit up counter i2c_timesim.vhd- post-route I2C simulation netlist
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Size: 889856 |
Author: benny |
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Description: 802.3an Ethernet 以太网络 LDPC Verilog 网表实现-802.3an Ethernet Ethernet LDPC Verilog netlist to achieve
Platform: |
Size: 914432 |
Author: |
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Description: ISCAS的benchmark 含有原理图，VHDL、VerilogHDL网表，测试数据等。
27-channel interrupt controller-ISCAS the benchmark contains schematic, VHDL, VerilogHDL netlist test data. 27-channel interrupt controller
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Size: 38912 |
Author: 大卫 |
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Description: 解决ORCAD无法输出网表问题 -ORCAD not solve the problem of output netlist
Platform: |
Size: 240640 |
Author: Jhon |
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Description: 低噪声放大器设计,使用电容反馈以及偏执电压,里面有详细的网表文件
自己做的,希望有用-Low-noise amplifier design, the use of feedback as well as the paranoid-voltage capacitors, which are detailed netlist file their own, and I hope useful
Platform: |
Size: 381952 |
Author: 陈鑫 |
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Description: PowerPCB教程简介
欢迎使用 PowerPCB 教程。本教程描述了PADS-PowerPCB 的绝大部分功能
和特点，以及使用的各个过程，这些功能包括：
· 基本操作
· 建立元件(Component)
· 建立板子边框线(Board outline)
· 输入网表(Netlist)
· 设置设计规则(Design Rule)
·元件(Part)的布局(Placement)
· 手工和交互的布线
· SPECCTRA全自动布线器(Route Engine)
·覆铜(Copper Pour)
· 建立分隔/混合平面层(Split/mixed Plane)
· Microsoft 的目标连接与嵌入(OLE)(Object Linking Embedding)
· 可选择的装配选件(Assembly options)
· 设计规则检查(Design Rule Check)
· 反向标注(Back Annotation)
· 绘图输出(Plot Output)
使用本教程后，你可以学到印制电路板设计和制造的许多基本知识。
你不必一次完成整个教程，如果在任何时候退出后，下次直接找到你要进入
的部分，继续学习本教程。
当你完成了本教程的学习后，可以参考在线帮助(On-line Help)以便得到更多
的信息。如果你需要附加的信息内容，你可以与PADS 在各地办事处或代理商取
得联系，以便得到更多的帮助。
欢迎使用PowerPCB进行PCB设计！-PowerPCB Tutorial Tutorial Introduction Welcome to PowerPCB. This tutorial describes the PADS-PowerPCB the vast majority of functions and features, and the use of the various processes, including: the establishment of the basic operation component (Component) to establish a border line board (Board outline) enter Table (Netlist) set design rules (Design Rule) component (Part) layout (Placement) manual and interactive cloth
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Size: 2532352 |
Author: 陈斌 |
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Description: 用于Ｐａｓ ＰＣＢ网表倒入Ａｌｌｅｇｒｏ ＣＩＳ检查／通道分配的小工具。
文件生成ＶＢＳ，再在ＣＩＳ中导入执行。-For Pas PCB netlist into Allegro CIS Inspection/channel allocation gadget. File Generation VBS, and then import the implementation of the CIS.
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Size: 3072 |
Author: Bomb |
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Description: 从cadence icfb 产生netlist skill 语言-Netlist generated from the cadence icfb
Platform: |
Size: 1024 |
Author: 程程 |
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Description: LAYOUT NETLIST FOR TANNER PRO:SIMPLE CURRENT MIRROR
Platform: |
Size: 1024 |
Author: adl |
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Description: PHILIPS LUXEON H NETLIST MODEL
Platform: |
Size: 159744 |
Author: JohnDoe |
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Description: Via Wizard 网表实力，方便在HFSS中过孔建模-Via Wizard Netlist
Platform: |
Size: 1024 |
Author: 菜SI_log |
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Description: 创建一个能够计算由给定技术库文件的行为网表文件指定的逻辑电路的关键路径的程序。-Creating a program capable of calculation the critical path for a logic circuit specified by a behavioral netlist file given a technology library file.
Platform: |
Size: 21504 |
Author: 骆扬 |
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