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Description: 查找表法，把数据事先写入RAM后，每当输入一个信号就等于输入一个地址进行查表，找出地址对应的内容，然后输出-Look-up table method, after prior written to RAM, the data input when a signal is input an address look-up table, find out the address corresponding to the content, and then output
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Size: 1024 |
Author: 周丹 |
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Description: 16-Bit Integrated Clock-LUT-DAC
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Size: 1041408 |
Author: makakeo |
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Description: Dual-Clock FIFO,
Depth: 256
Width: 32
USEDW: Y
FULLL:Y
EMPTY:Y-This is self-defined Dual-Clock FIFO, using logic lut resources.
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Size: 1024 |
Author: ylwang |
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Description: C编的停车场管理系统,用堆栈和队实现的,并加入了人性化设计,(C of parking lot management system, use the stack and team, and joined the humanized design,)
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Size: 12288 |
Author: Dorif
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Description: 6SV1.1B辐射传输模型，用于得到LUT(6SV1.1B radiative transfer model)
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Size: 1554432 |
Author: Caroline0989
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Description: 列举了四种方法扫描图像，分别是利用指针；迭代器；at操作符；和OpenCV自带的LUT方法。比较他们的用时。(how to scan images.copare the cosuming time.)
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Size: 5682176 |
Author: Terry灬
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Description: 遥感6s模拟程序，包括lut查找表，气溶胶反演的源代码，以及6s的运行程序(Remote sensing 6S simulation program)
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Size: 2482176 |
Author: lizhaolin |
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Description: 大气辐射传输模型,是Fortran语言编写的，可用来做大气校正或者建立查找表LUT,用来反演气溶胶(Radiative transfer model)
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Size: 1936384 |
Author: 月月_cxy |
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Description: FPGA应用底层开发的逻辑单元slice连线实现计数器的功能，包含代码及仿真(FPGA applies the logic unit slice connection that is developed at the bottom to realize the function of counter, including code and simulation.)
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Size: 6642688 |
Author: ltfy咖啡 |
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Description: 图像压缩是图像处理中的一个重要课题，在减少图像尺寸以实时传输和存储方面起着非常重要的作用。许多标准推荐使用DWT进行图像压缩。DWT的计算复杂度对基于DWT的图像压缩算法的实时使用提出了重大挑战。在本文中，我们提出了一种改进的提升方案来计算近似和详细的DWT系数。修正的方程使用右移运算符和6位乘法器。计算中的层级减少到一个，从而最小化延迟和增加吞吐量。ViTEX-5 FPGA上实现的设计工作在180 MHz，功耗小于1W的功率。该设计占用了FPGA上不到1的LUT资源。所开发的体系结构适合于FPGA平台上的实时图像处理。(Image compression is one of the prominent topics in image processing that plays a very important role in reducing image size for real-time transmission and storage. Many of the standards recommend the use of DWT for image compression. The computational complexity of DWT imposes a major challenge for the real-time use of DWT-based image compression algorithms. In this paper, we propose a modified lifting scheme for computing the approximation and detailed coefficients of DWT. The modified equations use, right shift operators and 6-bit multipliers. The hierarchy levels in computation are reduced to one thereby minimizing the delay and increasing throughput. The design implemented on Virtex-5 FPGA operates at 180 MHz and consumes less than 1W of power. The design occupies less than 1 of the LUT resources on FPGA. The architecture developed is suitable for real-time image processing on FPGA platform.)
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Size: 1473536 |
Author: asde198250 |
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