Description: 该工程是基于verilog hdl 语言编写的帧传输协议HDLC帧的发送端代码，会用QUATUSII的人都应该知道如何使用，希望能给你带来帮助-The project is based on the language verilog hdl frame transmission protocol HDLC frame of this generation - Codes will be used QUATUSII people should know how to use, in the hope of giving you helpful Platform: |
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Author:何丹萍 |
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Description: Verilog HDL硬件描述语言
01简介.PDF
02HDL指南.PDF
03语言要素.PDF
04表达式.PDF
05门电平模型化.PDF
06用户定义原语.PDF
07数据流模型化.PDF
08行为建模.PDF
09结构建模.PDF
10其它论题.PDF
11验证.PDF
12建模实例.PDF
13语法参考.PDF-Verilog HDL Hardware Description Language Introduction 01. PDF 02HDL Guide. PDF 0 3 language elements. PDF 04 expressions. PDF 05-level modeling. PDF 06 user-defined primitives. P DF 07 data flow modeling. PDF 08 behavior modeling. PDF 09 modeling structure. PDF 10 other topics . PDF 11 certification. PDF 12 model. PDF 13 syntax reference. PDF Platform: |
Size: 4837376 |
Author:高 |
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Description: 该工程是基于verilog hdl 语言编写的帧传输协议HDLC帧的发送端代码，会用QUATUSII的人都应该知道如何使用，希望能给你带来帮助-The project is based on the language verilog hdl frame transmission protocol HDLC frame of this generation- Codes will be used QUATUSII people should know how to use, in the hope of giving you helpful Platform: |
Size: 382976 |
Author:何丹萍 |
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Description: HDLC控制接收数据开始标志7E和去零模块，用于FPGA与E1相接，Verilog HDL语言编写-HDLC control began to receive data to the zero mark 7E and modules for use in FPGA and E1 phase, Verilog HDL language Platform: |
Size: 2048 |
Author:刘彻 |
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Description: HDLC控制协议中CRC校验码算法代码，为CRC16，Verilog语言-HDLC Control Protocol Code in the CRC checksum algorithm code for CRC16, Verilog language Platform: |
Size: 1024 |
Author:刘彻 |
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Description: verilog HDL语言编写的HDLC协议的IP核，包括通讯控制及CRC。-written in verilog HDL HDLC protocol IP core, including communications control and CRC. Platform: |
Size: 69632 |
Author:王强 |
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