Search - Counter

[Internet-Network] counter

Description: 用C++编写的计数器CGI程序，功能强大，运行速度快速可靠，计数器也可以隐藏，该CGI程序运行于WinNT/Intel平台-prepared by the Counter CGI program, a powerful, fast and reliable operating speed, counter can hide, The CGI program runs on WinNT / Intel platform
Platform: | Size: 107925 | Author: 林楠 | Hits:

[Other resource] 8051 Counter 0 Example Program

Description: 8051单片机的计数器0的操作程序源代码-8051 0 counter the source code for the procedure
Platform: | Size: 10817 | Author: 吴松 | Hits:

[Other resource] counter&adder

Description: counter and adder program by vhdl. Just enjoy it!-counter and adder program by VHDL. Just enj oy it!
Platform: | Size: 1670 | Author: simon | Hits:

[Other resource] MCU-counter

Description: 用verilog实现单片机计数器用verilog实现单片机计数器-MCU with verilog counter with MCU counter verilog
Platform: | Size: 748106 | Author: ukh | Hits:

[Other resource] counter

Description: 1.40种记数器图片样式自由选择，并且可以方便地增加记数器图片样式。 2.可以设置计数器显示数字,显示位数,计数器是否隐藏等。 3.页面显示记数和唯一IP记数两种记数模式。 4.可以记录来访客的来源IP地址和来源页面信息,在线人数。 5.每月、每天和每小时的访问数据统计。 6.搜索引擎统计，还可以自己定义搜索引擎。 7.注册用户找回密码功能。 8.多用户计数器，具有管理注册用户功能。 9.系统会自动删除过多的以前的无用的来源和在线记录，保证系统快速稳定运行,还可以在线压缩数据库。 10.增加计数器图片样式的方法：把新的计数器图片复制到qqcf_counterpic目录，然后设置样式数量即可。 11.安全性：密码MD5加密，注册、登陆使用验证码，完全防Sql注入 -1.40 Species Register Photo style freedom of choice, and can easily increase Register Photo pattern. 2. Can set counter shows the figures show that the median counter whether such hidden. 3. Page shows that in mind, and only a few IP counting both counting patterns. 4. Visitors can be recorded to the source IP address and source of pages of information, the number of online. 5. Monthly, daily and hourly statistics visit. 6. Search engine statistics, but also their own definition of search engines. 7. Registered users retrieve cryptographic functions. 8. Multi-user counter, with a registered user management functions. 9. The system automatically deleted before too many useless sources and online records, ensuring rapid and stable operating system, Compression can also online database. 10. P
Platform: | Size: 420961 | Author: 陈华 | Hits:

[WEB Code] (counter)

Description: NET网站访问统计系统(counter)，平台asp.net+c#，显示网站访问统计的简单例子。-NET website statistics system (counter), the platform Asp. Net c #, Statistics show that the site was visited by a simple example.
Platform: | Size: 1018073 | Author: 陈是 | Hits:

[VHDL-FPGA-Verilog] Verilog 编写的计数器

Description: 用 verilog 编写的updown counter
Platform: | Size: 393581 | Author: sevenprince | Hits:

[Other] Time-counter

Description: 基于Visual C++而编写的时间计数器程序源代码-Time counter is based on Visual C++.I hope it is useful for you !
Platform: | Size: 784 | Author: 李旋 | Hits:

[ELanguage] dsasmsrc

Description: 一个反汇编程序源码- A counter- assembly program source code
Platform: | Size: 632832 | Author: 站长 | Hits:

[Other] counter

Description: 基于php+mysql多用户多风格防刷新计数器- Multiuser multi- styles guard against based on php the mysql renovate the counter
Platform: | Size: 8192 | Author: 黎明 | Hits:

[SCM] C51智能反编译器

Description: C51智能反编译器-C51 intelligence counter- compiler
Platform: | Size: 252928 | Author: 林松 | Hits:

[VHDL-FPGA-Verilog] counter

Description: 用VHDL语言编写COUNTER-FPGA VHDL COUNTER
Platform: | Size: 113664 | Author: CG | Hits:

[matlab] counter

Description: Counter in Matlab we can create a counter on matlab with this program
Platform: | Size: 1024 | Author: chris | Hits:

[VHDL-FPGA-Verilog] counter

Description: -- Mod-16 Counter using JK Flip-flops -- Structural description of a 4-bit binary counter. -- The first two design entities describe a JK flip-flop and a 2-input AND gate respectively. -- These are then packaged together along with a signal named tied_high into a package named jkpack . -- The counter design uses the package jkpack , giving it access to the components and the signal declared within the package. -- The flip-flops and AND-gates are wired together to form a counter. -- Notice the use of the keyword OPEN to indicate an open-cct output port. -- some syntax can t be synthesized,it s for simulation only,such as "AFTER 5 ns"--- Mod-16 Counter using JK Flip-flops -- Structural description of a 4-bit binary counter. -- The first two design entities describe a JK flip-flop and a 2-input AND gate respectively. -- These are then packaged together along with a signal named tied_high into a package named jkpack . -- The counter design uses the package jkpack , giving it access to the components and the signal declared within the package. -- The flip-flops and AND-gates are wired together to form a counter. -- Notice the use of the keyword OPEN to indicate an open-cct output port. -- some syntax can t be synthesized,it s for simulation only,such as "AFTER 5 ns"
Platform: | Size: 1024 | Author: jgc | Hits:

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[Internet-Network] counter

[Other resource] 8051 Counter 0 Example Program

[Other resource] counter&adder

[Other resource] MCU-counter

[Other resource] counter

[WEB Code] (counter)

[VHDL-FPGA-Verilog] Verilog 编写的计数器

[Other] Time-counter

[ELanguage] dsasmsrc

[Other] counter

[SCM] C51智能反编译器

[VHDL-FPGA-Verilog] counter

[matlab] counter

[VHDL-FPGA-Verilog] counter

[matlab] Automatic-Coin-Counter-Matlab-Code

[VHDL-FPGA-Verilog] Adder and Counter VHDL

[ARM-PowerPC-ColdFire-MIPS] led on off-waiting counter

[VHDL-FPGA-Verilog] counter

[VHDL-FPGA-Verilog] counter

[VHDL-FPGA-Verilog] bcd counter

CodeBus www.codebus.net

Category

Source Code

Web/Internet

Develop Tools

Document

Other

Search in results

OS

Platform

Language

File Type

Search list

[Internet-Network] counter

[Other resource] 8051 Counter 0 Example Program

[Other resource] counter&adder

[Other resource] MCU-counter

[Other resource] counter

[WEB Code] (counter)

[VHDL-FPGA-Verilog] Verilog 编写的 计数器

[Other] Time-counter

[ELanguage] dsasmsrc

[Other] counter

[SCM] C51智能反编译器

[VHDL-FPGA-Verilog] counter

[matlab] counter

[VHDL-FPGA-Verilog] counter

[matlab] Automatic-Coin-Counter-Matlab-Code

[VHDL-FPGA-Verilog] Adder and Counter VHDL

[ARM-PowerPC-ColdFire-MIPS] led on off-waiting counter

[VHDL-FPGA-Verilog] counter

[VHDL-FPGA-Verilog] counter

[VHDL-FPGA-Verilog] bcd counter

CodeBus www.codebus.net

[VHDL-FPGA-Verilog] Verilog 编写的计数器