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Description: amd和intel cpu的各种型号及具体参数列表
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Size: 46080 |
Author: fuqm |
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Description: 包括1) 时钟发生器
2) 指令寄存器
3) 累加器
4) RISC CPU算术逻辑运算单元
5) 数据控制器
6) 状态控制器
7) 程序计数器
8) 地址多路器
-1) clock generator 2) instruction register 3) accumulator 4) RISC CPU arithmetic logical unit 5) of the data controller 6) state controller 7), the program counter 8) address multiplexer
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Size: 440320 |
Author: liuying |
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Description: 16位的CPU的VHDL程序~~还有附加的生成波形,可以应用于课程设计中-16-bit CPU, VHDL ~ ~ There are additional procedures for generating waveforms, can be applied to curriculum design
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Size: 1053696 |
Author: liuying |
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Description: VHDL16位cpu,能实现加减法移动等指令-vhdl 16 cpu,include add,sub,move and so on.
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Size: 19456 |
Author: 王军 |
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Description: Grabbing the CPU ID in delphi
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Size: 7168 |
Author: tool63 |
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Description: VC编程控制CPU使用率,使使用率呈函数曲线-VC programming control CPU usage, so that the utilization rate was a function of curve
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Size: 1167360 |
Author: 孙芸芸 |
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Description: CPU实时监控程序,能够对计算机CPU的消耗情况进行实时监控,并且以图形及百分比进行显示.-CPU solid hour supervise and control procedure, can to the depletion circumstance of calculator CPU carry on solid hour supervise and control, and carry on a manifestation by the sketch and the percentage.
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Size: 4096 |
Author: 魏吏民 |
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Description: 一个完整的流水CPU设计,quartus平台,Verilog实现-CPU design a complete water, quartus platform, Verilog realization
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Size: 1100800 |
Author: 涯 |
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Description: 16位简单cpu用VHDL语言实现。里面有好几个的》-16-bit cpu with a simple VHDL language. There are several of the "
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Size: 3181568 |
Author: pjj |
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Description: 一个多周期CPU的完整设计,quartus平台,Verilog实现,内含实验报告,和详细的各模块功能表-Complete a multi-cycle CPU design, quartus platform, Verilog implementation, includes lab reports, and a detailed menu of each module
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Size: 6606848 |
Author: 涯 |
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Description: 组成原理实验~简单cpu的设计~基于EDA环境下的-Composition Theory Experiment Design ~ ~ Simple cpu EDA environment based on
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Size: 724992 |
Author: lynn |
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Description: CPU使用率监视
1.监视CPU占用率(动态现实托盘区图标)
2.显示内存情况
3.快速启动 windows任务管理器-CPU utilization monitoring 1. Monitoring CPU usage (dynamic reality tray icon) 2. Display memory situation 3. Quick Start windows task manager
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Size: 172032 |
Author: eejin |
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Description: CPU监控程序VB版,显示适时曲线,vb源码-failed to translate
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Size: 67584 |
Author: kingcom |
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Description: cpu design in verilog
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Size: 275456 |
Author: ujjwal |
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Description: CPU设计,包含基本的指令集,能执行简单的程序。考虑了CPU,寄存器,存储器和指令集之间的关系。即读写寄存器,读写存储器和执行指令。-CPU design, including basic instruction set, to execute a simple program. Consider the CPU, registers, memory, and the relationship between instruction sets. That read and write registers, read and write memory and execution.
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Size: 3383296 |
Author: ilmf |
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Description: Windows Hook Library (Any CPU)
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Size: 16384 |
Author: xacker-87 |
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Description: 一款用VB6编写的检测CPU使用率的软件源码,控制整个软件CPU使用率-A written test with VB6 source software CPU utilization, CPU utilization control the entire software
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Size: 2048 |
Author: 容均致 |
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Description: 一个简单的CPU设计,支持add,sub,mvi,mv四条指令,用Verilog语言编写,在Quratus II上编译通过,仿真正确。-A simple CPU design, support add, sub, mvi, mv four instructions, with the Verilog language, compiled by the Quratus II, the simulation is correct.
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Size: 931840 |
Author: 姜涛 |
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Description: 5 stage pipeline CPU, verilog HDL code-5 stage pipeline CPU
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Size: 2048 |
Author: dylan |
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Description: 读取计算机硬件信息,如CPU序列号,硬盘编号等-get hardware information,such as cpu serial No.,harddisk serial No., etc.
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Size: 416768 |
Author: resun li |
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