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[Other] ASIC

Description: A bood book on Application Specific Integrated Circuit.
Platform: | Size: 3958784 | Author: Jabir Khan | Hits:

[Books] Advanced.ASIC.Chip.Synthesissys

Description: The emphasis of this book is on real-time application of Synopsys tools, used to combat various problems seen at VDSM geometries. Readers will be exposed to an effective design methodology for handling complex, submicron ASIC designs. Significance is placed on HDL coding styles, synthesis and optimization, dynamic simulation, formal verification, DFT scan insertion, links to layout, physical synthesis, and static timing analysis. At each step, problems related to each phase of the design flow are identified, with solutions and work-around described in detail. In addition, crucial issues related to layout, which includes clock tree synthesis and back-end integration (links to layout) are also discussed at length. Furthermore, the book contains in-depth discussions on the basics of Synopsys technology libraries and HDL coding styles, targeted towards optimal synthesis solution.
Platform: | Size: 2244608 | Author: wsea | Hits:

[Other] ASIC

Description: ASIC中的异步时序设计文档，提供了ASIC设计中处理异步时序的方法-ASIC design of asynchronous sequential documents, provided the ASIC design methodology to deal with asynchronous timing
Platform: | Size: 413696 | Author: 田涛 | Hits:

[VC/MFC] ASIC_Primer

Description: LSI Logic ASIC Primer
Platform: | Size: 386048 | Author: kajal | Hits:

[VHDL-FPGA-Verilog] multiclock_whitepaper

Description: ASIC中多时钟域处理方法白皮书。描述了ASIC设计/FPGA设计中跨时钟域信号的处理方法。-ASIC in the multi-clock domain approach the White Paper. Describes the ASIC design/FPGA design in the inter-clock domain signal processing methods.
Platform: | Size: 273408 | Author: forrest1 | Hits:

[VHDL-FPGA-Verilog] ASIC_Design_Flow_Tutorial_with_synopsys

Description: Tutorial from VCS to IC Compiler for ASIC design using synopsys tool. .
Platform: | Size: 4128768 | Author: Kang | Hits:

[Other] Morgan.Kaufmann.ASIC.and.FPGA.Verification.A.Guid

Description: ASIC and FPGA Verification: A Guide to Component Modeling is organized so that it can be read linearly from front to back. Chapters are grouped into four parts: Intro- duction, Resources and Standards, Modeling Basics, and Advanced Modeling. Each part covers a number of related modeling concepts and techniques, with individ- ual chapters building upon previous material. -ASIC and FPGA Verification: A Guide to Component Modeling is organized so that it can be read linearly from front to back. Chapters are grouped into four parts: Intro- duction, Resources and Standards, Modeling Basics, and Advanced Modeling. Each part covers a number of related modeling concepts and techniques, with individ- ual chapters building upon previous material.
Platform: | Size: 1455104 | Author: Onproxy | Hits:

[Other] Virtuoso-XL_Layout_Editor

Description: Virtuoso-XL_Layout_Editor best free cadence tutorial material guide in design asic and soc
Platform: | Size: 2922496 | Author: loktikvj | Hits:

[Books] ASIC

Description: 很好的设计书，大家可以一起分享一下，上传咯-designbook
Platform: | Size: 1304576 | Author: 沙飞 | Hits:

[VHDL-FPGA-Verilog] dqpsk_demodulator_f_pa

Description: FSK QPSK DQPSK 等verilog 源码 及asic实现-FSK QPSK DQPSK and asic implementation such as verilog source
Platform: | Size: 63488 | Author: nie | Hits:

[Other] ASIC_Design_Flow_Tutorial

Description: ASIC Design Flow Tutorial，讲解ASIC设计流程的超详细文档。-ASIC Design Flow Tutorial, explain the ASIC design flow, ultra-detailed documentation.
Platform: | Size: 4002816 | Author: 贾启祥 | Hits:

[VHDL-FPGA-Verilog] SystemVerilogImplicitPorts

Description: The Accellera SystemVerilog language[3] includes two new features designed to remove much of the tedium and verbosity related to building top-level ASIC and FPGA designs from instantiated sub-blocks. These enhancements permit one of two forms of implicit port connectionsThe Accellera SystemVerilog language[3] includes two new features designed to remove much of the tedium and verbosity related to building top-level ASIC and FPGA designs from instantiated sub-blocks. These enhancements permit one of two forms of implicit port connections-The Accellera SystemVerilog language[3] includes two new features designed to remove much of the tedium and verbosity related to building top-level ASIC and FPGA designs from instantiated sub-blocks. These enhancements permit one of two forms of implicit port connections
Platform: | Size: 63488 | Author: 陈斌 | Hits:

[matlab] ASIC_LIB

Description: ASIC设计中常用的运算模块，如加减，常系数乘法，截断，饱和等。-some modules used in ASIC design.
Platform: | Size: 7168 | Author: liubo | Hits:

[Software Engineering] ASIC

Description: ASIC的异步时序设计，很有用，关于fifo-Asynchronous timing ASIC design, very useful
Platform: | Size: 250880 | Author: 徐寅晖 | Hits:

[VHDL-FPGA-Verilog] MAC_Transceiver

Description: MAC(以太网媒体访问控制)是以太网IEEE 802.3协议规定的数据链路层的一部分,使用FPGA替代ASIC,实现以太网MAC功能非常实用。能够实现硬件系统多路多端口的以太网接入,并在自行开发需要以太网接入的嵌入式处理器设计中得到应用。具体探讨以太网MAC的功能定义,使用FPGA实现以太网MAC的方法,对以太网的相关应用设计具有指导作用。 -MAC (Ethernet Media Access Control) is a protocol under the IEEE 802.3 Ethernet data link layer part of the use of FPGA alternative ASIC, Ethernet MAC functionality is very useful. Hardware system to achieve multi-channel multi-port Ethernet access and Ethernet access to its own development needs of embedded processor design has been applied. To specifically explore the functional definition of the Ethernet MAC using FPGA Ethernet MAC method, the design of Ethernet-related applications guide.
Platform: | Size: 1572864 | Author: 陈辉 | Hits:

[Crack Hack] ASIC

Description: Design and simulation of ASIC-based system control Application to Direct Torque Control of Induct
Platform: | Size: 252928 | Author: inouir | Hits:

[VHDL-FPGA-Verilog] Design-Reuse-Methodology-For-Asic-And-Fpga-Designe

Description: asic/fpga设计复用技术 Design-Reuse-Methodology-For-Asic-And-Fpga-Designers-Design-Reuse-Methodology-For-Asic-And-Fpga-Designers
Platform: | Size: 184320 | Author: yin zhigang | Hits:

[VHDL-FPGA-Verilog] ASIC.and.FPGA.Verification.A.Guide.to.Component.Mo

Description: ASIC的FPGA模型设计，VHDL版 英文原版书籍-ASIC.and.FPGA.Verification.A.Guide.to.Component.Modeling.Morgan.Kaufmann
Platform: | Size: 1356800 | Author: Craftor | Hits:

[Other] Advanced_ASIC_Chip_Synthesis

Description: ADVANCED ASIC CHIP SYNTHESIS---Physical Compiler™ and PrimeTime 英文电子书。-EBOOK OF THE Using Synopsys® Design Compiler™ Physical Compiler™ and PrimeTime--
Platform: | Size: 4080640 | Author: john | Hits:

[VHDL-FPGA-Verilog] ASIC_VHDL_FPGA_design_lectureNotes

Description: 这是美国普渡大学（Purdue University West Lafayette)ASIC design 的课件完整版！带事例和讲解的非常好的VHDL学习材料！含有vhdl 基础知识，设计步骤，UART, RTL,Test Bench 以及测试和调试，DEBUG等各种VHDL设计者必学知识！-This is Purdue University (USA) ECE 337 ASIC design class lecture notes! very classic! The content include basics of vhdl, design process, UART design, RTL design, test and debug etc,etc VERY helpful to VHDL learners. A MUST SEE !
Platform: | Size: 10332160 | Author: zhou | Hits:
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