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Description: 本文档用于使用systemverilog系统硬件描述语言做ASIC设计，深入浅出，易懂(The doc is using systemverilog system harward description language to do ASIC design.The doc is easy to read,for new bird in this fact.)
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Size: 2354176 |
Author: zuige2011
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Description: mux四选一及译码器：MUX电路在数字集成电路被广泛使用，作为寄存器或者其他电路的输入选择控制。也是ASIC设计中的基本门电路之一。(MUX four selection one and decoder)
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Size: 2048 |
Author: W*ei
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Description: Mentor公司的ModelSim是业界最优秀的HDL语言仿真软件，它能提供友好的仿真环境，是业界唯一的单内核支持VHDL和Verilog混合仿真的仿真器。它采用直接优化的编译技术、Tcl/Tk技术、和单一内核仿真技术，编译仿真速度快，编译的代码与平台无关，便于保护IP核，个性化的图形界面和用户接口，为用户加快调错提供强有力的手段，是FPGA/ASIC设计的首选仿真软件。(Mentor's ModelSim, the industry's best HDL language simulation software, offers a friendly simulation environment and is the industry's only single-core simulator supporting VHDL and Verilog mixed simulations. It uses direct optimization of the compiler technology, Tcl / Tk technology, and a single kernel simulation technology, compile and emulate fast, compiled code has nothing to do with the platform, easy to protect IP core, personalized graphical interface and user interface to speed up the user to debug wrong Provide a powerful means of choice for FPGA / ASIC design simulation software.)
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Size: 523264 |
Author: 冰激凌很牛
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Description: firmware100.bin from asic box
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Size: 1855488 |
Author: deathknight226 |
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Description: kern.bin image from asic box
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Size: 1424384 |
Author: deathknight226 |
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Description: os.bin os extra applications from asic box
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Size: 1055744 |
Author: deathknight226 |
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Description: tmp.bin from asic box
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Size: 1152000 |
Author: deathknight226 |
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Description: extra.bin additional files from asic box
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Size: 191488 |
Author: deathknight226 |
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Description: guide book to fpgas and hdl
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Size: 4063232 |
Author: Sensei |
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Description: Book about low power asic design.
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Size: 1840128 |
Author: nguyentl |
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Description: 本文首先回顾了LDPC码的发展历程和现状，介绍了LDPC码检验矩阵的构造、编
译码原理。在对编译码作了深入探讨和分析后，接着进行了RU算法编码和长码编码
的FPGA实现;根据二叉树的性质，提出了一种长码编码的ASIC优化设计的方法，节省
了大量硬件资源;论文详细阐述了CORDIC算法原理以及LDPC码译码中所采用的指
数函数和反双曲正切函数的FPGA实现:CORDIC内核及前后处理单元设计、仿真、综
合及数据分析，这对LDPC码的译码具有很重要的意义，为用数字VLSI来实现LDPC的
译码奠定了基础。同时在基于校验矩阵的环路检测定理基础上，将校验矩阵转化为转
移概率矩阵，详细分析并提出了一种基于转移概率矩阵的围长检测方法，并对其进行
了理论证明，具有很好的围长检测效果，以及状态分类判别。(Research and implementation of LDPC coding and decoding technology)
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Size: 1529856 |
Author: 斯蓝蓝 |
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Description: MIPS32 M4KTM内核是一种高性能，低功耗，32位MIPS RISC处理器内核，适用于定制的硅片系统应用。 该内核是为希望将其自定义逻辑和外围设备与高性能RISC处理器快速集成的半导体制造公司，ASIC开发人员和系统OEM设计的。
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Size: 868321 |
Author: luistenu |
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Description: ICCAD 2004 Faraday Mixed-size Benchmarks with routing information
Faraday Corp. recently released three benchmarks, originally intended
for comparisons between structured and conventional ASICs. We apply to
these benchmarks a standard ASIC design flow to generate five
mixed-size designs. Faraday benchmarks include three commonly-used
functional blocks: (I) 16-bit DSP, (II) 32-bit RISC CPU and (III)
DMA. Other details on these benchmarks such as the EDA Tools used by
Faraday, implementation conditions, settings etc. can be found in on
the faraday web-site. To minimize the impact of routing on the results
of the accounted placement approaches, we avoid clock-tree generation
and power routing in our flows. However, both clock-trees and power
rails can be built on theses benchmarks. Following is the description
of our ASIC flow which we used for generating the mixed-size
benchmarks from the original netlists.
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Size: 7427884 |
Author: ahimsafollower@gmail.com |
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