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[VHDL-FPGA-Verilog] USB2_0

Description: USB2_0设备控制器IP核的AHB接口技术。-USB2_0 Device Controller IP Core AHB interface technology.
Platform: | Size: 288768 | Author: 陈锴 | Hits:

[VHDL-FPGA-Verilog] AHB_Decoder

Description: 该源码包包含AHB译码模块及其测试文件。AHB译码器用来将Master发出的地址信号进行译码以选择确定的从设备对传输进行响应。-The source package contains the AHB decoder module and its test file. Master AHB decoder is used to send signals to decode the address to select a determined response from the device on the transmission.
Platform: | Size: 3072 | Author: 杨宗凯 | Hits:

[Software Engineering] AHBtoAPB

Description: AHBtoAPB设计基于AMBA总线协议的APB Bridge设计-AHB to APB designThe AHB to APB bridge interface is an AHB slave. When accessed (in normal operation or system test) it initiates an access to the APB.
Platform: | Size: 114688 | Author: 李雷 | Hits:

[VHDL-FPGA-Verilog] AMBA_design_kit

Description: AMBA design kit doc, which is used to guide the design of ahb/apb based arm soc/mcu
Platform: | Size: 909312 | Author: brucew | Hits:

[Software Engineering] AHB

Description: advanced high performance bus discrciption
Platform: | Size: 871424 | Author: vamsi | Hits:

[Other Embeded program] AMBA

Description: AMBA 协议是用于连接和管理片上系统 (SoC) 中功能模块的开放标准和片上互连规范。它有助于首次开发带有大量控制器和外设的多处理器设计。AMBA 通过使用 AXI、AHB、APB 和 ATB 的规范对 SoC 模块的共同主干进行定义，这有助于设计的重复使用。-AMBA protocol is used to connect and manage on-chip (SoC) functional modules of open standards and on-chip interconnect specifications. It helps the development of multi-processor design with a large number of controllers and peripherals for the first time. Definition of the AMBA specification of AXI, AHB, APB and ATB common backbone for SoC modules, which helps design reuse.
Platform: | Size: 519168 | Author: liyapei | Hits:

[SCM] IO_toggle

Description: This example describes how to toggle the GPIO pins connected on AHB bus.
Platform: | Size: 2048 | Author: asdf | Hits:

[SCM] SYS_tick

Description: This example shows how to configure the SysTick to generate a time base equal to 1 ms. The system clock is set to 168 MHz, the SysTick is clocked by the AHB clock (HCLK).
Platform: | Size: 2048 | Author: asdf | Hits:

[VHDL-FPGA-Verilog] psram_controller

Description: PSRAM_CONTROLLER THE CONTROLLER IS USED FOR PSRAM AND AHB BUS IT HAVE FINISH SIMULATION OK FPGA VERIFY OK SYNTHSIS DESIGN COMPILER SPEED TO 200 mhz -THE CONTROLLER IS USED FOR PSRAM AND AHB BUS IT HAVE FINISH SIMULATION OK FPGA VERIFY OK SYNTHSIS DESIGN COMPILER SPEED TO 200 mhz
Platform: | Size: 3072 | Author: steven.tung | Hits:

[VHDL-FPGA-Verilog] wb_to_amba_latest[1].tar

Description: ahb总线到wishbone总线的桥接器，包括一个testbench,该版本暂不支持burst操作-A AHB master to WishBone slave bridge along with a basic testbench is included. Burst in not yet supported
Platform: | Size: 11264 | Author: hxr | Hits:

[Other] AHBPAPB

Description: AMBA总线的AHB+APB源程序，供初学者学习。-Verilog for AHB and APB
Platform: | Size: 37888 | Author: aaa | Hits:

[Windows Develop] ACODEH

Description: AHB总线下的slave ramm的verilog代码 -Verilog code of the AHB bus slave ramm
Platform: | Size: 1024 | Author: tb | Hits:

[Other] ahbctrl

Description: AMBA2.0,ahb总线控制器的实现，来自leon3开源代码-AMBA2.0, the implementation of ahb bus controller, from leon3 open source code
Platform: | Size: 19456 | Author: 张鹏 | Hits:

[VHDL-FPGA-Verilog] ddr2

Description: leon3系统中ddr2控制器的相关代码（还包包括存储器的仿真模型），该控制器可以与amba2.0的ahb总线相连，机构比较复杂，代码量很大-ddr2 controller code (package includes the memory of the simulation model) leon3 system, the controller can with amba2.0 the ahb bus connected to more complex institutions, the amount of code
Platform: | Size: 219136 | Author: 张鹏 | Hits:

[VHDL-FPGA-Verilog] AMBA_SPEC

Description: AMBA标准2.0版本，包括AHB，APB和ASB-AMBA standard specfication rev2.0, including AHB, APB, and ASB
Platform: | Size: 887808 | Author: joy | Hits:

[SCM] SysTick

Description: STM32官方例程，滴答时钟，可利用系统内的滴答进行延时，更加准确-This example shows how to configure the SysTick to generate a time base equal to 1 ms. The system clock is set to 24 MHz on Value line devices and to 72 MHz on other devices, the SysTick is clocked by the AHB clock (HCLK). A "Delay" function is implemented based on the SysTick end-of-count event. Four LEDs are toggled with a timing defined by the Delay function.
Platform: | Size: 13312 | Author: 峥嵘 | Hits:

[VHDL-FPGA-Verilog] dma_ahb

Description: 挂靠在AMBA2.0的AHB总线上的DMA装置，用于直接发起数据传输。-Anchored the DMA devices the AHB bus AMBA2.0, for initiating data transfer.
Platform: | Size: 750592 | Author: jiangxingtong | Hits:

[Compress-Decompress algrithms] ahb2wishbone_latest.tar

Description: AHB to Wishbone memory interface VHDL source code
Platform: | Size: 10638336 | Author: cyf | Hits:

[VHDL-FPGA-Verilog] AMBA_AHB.rar

Description: amba AHB coding in verilog HDL and integrating with AHB to AXI Brigde,amba AHB coding in verilog HDL and integrating with AHB to AXI Brigde
Platform: | Size: 5120 | Author: videv | Hits:

[Other] apb_bridge

Description: AMBA AHB总线上连接慢速设备的slave,通过 apb_bridge桥实现AHB到APB的转换-AMBA apb_bridge
Platform: | Size: 2048 | Author: 朱哲 | Hits:
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