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[VHDL-FPGA-Verilog] FPGA_tbench

Description: 一个actel公司fpga测试台程序，经过编译可以成功运行-A actel company fpga test program can run successfully compiled
Platform: | Size: 3072 | Author: guxinyu | Hits:

[VHDL-FPGA-Verilog] NAND_Flash_Interface_DF

Description: actel NAND Flash Interface Design Example
Platform: | Size: 2597888 | Author: akjfklaskdfj | Hits:

[WEB Code] phpupload-v1.0

Description: 爱特文件中转上传是用一个空间给另一个空间传文件的，主要是用来给那些不支持curl\allow_url_fopen的空间实现文件快速上传的，当然同空间也是可以的。-Actel file transfer upload is to transfer a file with a space to another space, mainly used to support those who do not curl, \ allow_url_fopen is space realization of the file quick uploads, of course, the same space can.
Platform: | Size: 7168 | Author: 老鬼 | Hits:

[Program doc] IGLOO_nano_DS

Description: Actel公司的IGLOO—NANO系列FPGA，其使用文档及参数说明-Actel Corporation IGLOO-NANO Series FPGA, use the document and the parameters
Platform: | Size: 4301824 | Author: wj | Hits:

[Program doc] IGLOO_nano_UG

Description: Actel公司的IGLOO—NANO系列FPGA，其用户使用手册及系列器件对比-Actel Corporation IGLOO-NANO Series FPGA, its user manual and a series of devices compared
Platform: | Size: 13244416 | Author: wj | Hits:

[Windows Develop] Vsteepper_motH

Description: 步进电机 VHDL 控制，整步 半半步 细分 actel FPGA使用 -VHDL control of stepper motor, whole step, half half step segments actel FPGA use
Platform: | Size: 1190912 | Author: cpdcoder | Hits:

[SCM] Actel_001112000

Description: PROTEL 99SE元器件库， Actel.ddb文件-PROTEL 99SE components library
Platform: | Size: 133120 | Author: peter | Hits:

[VHDL-FPGA-Verilog] A3P600-PQG208

Description: Actel FPGA A3P600最小系统原理图，包含JTAG 、电源和封装 -Actel FPGA A3P600 minimum system schematics, including JTAG, power and packaging
Platform: | Size: 47104 | Author: DAFEI | Hits:

[VHDL-FPGA-Verilog] FSK

Description: 推荐一个FSK解调工程，用Actel FPGA 实现的比较通用，VHDL 源代码。-Recommended Actel FPGA implementation FSK demodulator engineering, more generic, VHDL realization.
Platform: | Size: 2861056 | Author: DAFEI | Hits:

[VHDL-FPGA-Verilog] ADC_3Channal

Description: Actel FPGA 3通道同时采样程序-Actel FPGA 3 Channel Sample Program
Platform: | Size: 924672 | Author: 匡工 | Hits:

[VHDL-FPGA-Verilog] A3P40_ProASIC3

Description: ProASIC3, the third-generation family of Actel flash FPGAs, offers performance, density, and features beyond those of the ProASICPLUS® family. Nonvolatile flash technology gives ProASIC3 devices the advantage of being a secure, low-power, single-chip solution that is live at power-up (LAPU). ProASIC3 is reprogrammable and offers time-to-market benefits at an ASIC-level unit cost. These features enable designers to create high-density systems using existing ASIC or FPGA design flows and tools. -ProASIC3, the third-generation family of Actel flash FPGAs, offers performance, density, and features beyond those of the ProASICPLUS® family. Nonvolatile flash technology gives ProASIC3 devices the advantage of being a secure, low-power, single-chip solution that is live at power-up (LAPU). ProASIC3 is reprogrammable and offers time-to-market benefits at an ASIC-level unit cost. These features enable designers to create high-density systems using existing ASIC or FPGA design flows and tools.
Platform: | Size: 1564672 | Author: laolixue | Hits:

[VHDL-FPGA-Verilog] PA3_E_FROM_AN

Description: actel flash rom使用 actel flash rom使用-actel flash rom actel flash rom
Platform: | Size: 165888 | Author: 何莉 | Hits:

[Windows Develop] TFT_Keil

Description: actel公司smartfusion系列TFT-LCD显示的keil工程函数库-Actel Company SmartFusion Series TFT-LCD display keil project library
Platform: | Size: 664576 | Author: zengjian | Hits:

[VHDL-FPGA-Verilog] A3P250_Prj

Description: 完整的工程文件，基于actel公司的A3P250开发板，工程内包含bench文件，便于仿真-Complete engineering documents, based on actel s A3P250 development board, the project contains bench file for easy simulation
Platform: | Size: 804864 | Author: 惠言 | Hits:

[VHDL-FPGA-Verilog] CS5361_DAT

Description: CS5361 ADC 驱动程序,其中还有时钟部分,这里是数据采集部分. 使用VerilogHDL编写,在Libero中编译,使用Actel芯片测试通过.-CS5361 ADC drivers, of which there are clock parts, here is the data collection using VerilogHDL written, compiled in Libero using Actel chip test.
Platform: | Size: 1024 | Author: 王刚 | Hits:

[Other] sspcs_V1.0_hdl

Description: 固态电源控制器 宽电压 大电流 actel sspcs源代码-Solid State Power Controller Wide voltage and high current actel sspcs source code
Platform: | Size: 3072 | Author: johu | Hits:

[Compress-Decompress algrithms] aite_fileadmin_v2.0

Description: 爱特网站文件专家 01.文件批量压缩功能 02.批量网址获取文件 爱特文件官方更新:http://www.debao21.com 爱特文件专家使用了Pclzip和Archive_Tar 爱特文件专家除此库之外均为原创编码 -Actel website files specialists 01. Batch file compression feature 02. Batch file URL for file Actel official update: http://www.debao21.com Aite file using Pclzip experts and experts in addition Archive_Tar Actel files outside the library are original coding
Platform: | Size: 54272 | Author: aa768228 | Hits:

[VHDL-FPGA-Verilog] CoreFIR_RTL-3.0

Description: actelIP核 的fircore Core Generator – Executable File Outputs Run-Time Library (RTL) Code and Testbench Based on Input Parameters – Self-Checking – Executable Tests Generated Output against Algorithm • Distributed Arithmetic (DA) Algorithm – Multiplier-Free Computation – Low Cost – Optimized for Actel FPGAs • Folding Architecture to Minimize Design Size – Serialized Computation when System Clock Rate is Faster than the Data Sample Rate • Efficient Structure Using Embedded RAMs – Lookup Tables Utilize Embedded RAMs • On-Chip DA Lookup Table Generator for FPGA with Embedded RAMs • Embedded RAMs Initialized as DA Lookup Table • DA Lookup Table ROM Synthesis for FPGA without Embedded RAMs • Multiple DA lookup Tables to Split Large Number of Taps • Actel FPGA-Optimized RTL Code • Supports 2 to 128 Taps • 1- to 32-Bit Input Data and Coefficient Precision-actelIPcore fircore Core Generator – Executable File Outputs Run-Time Library (RTL) Code and Testbench Based on Input Parameters – Self-Checking – Executable Tests Generated Output against Algorithm • Distributed Arithmetic (DA) Algorithm – Multiplier-Free Computation – Low Cost – Optimized for Actel FPGAs • Folding Architecture to Minimize Design Size – Serialized Computation when System Clock Rate is Faster than the Data Sample Rate • Efficient Structure Using Embedded RAMs – Lookup Tables Utilize Embedded RAMs • On-Chip DA Lookup Table Generator for FPGA with Embedded RAMs • Embedded RAMs Initialized as DA Lookup Table • DA Lookup Table ROM Synthesis for FPGA without Embedded RAMs • Multiple DA lookup Tables to Split Large Number of Taps • Actel FPGA-Optimized RTL Code • Supports 2 to 128 Taps • 1- to 32-Bit Input Data and Coefficient Precision
Platform: | Size: 1051648 | Author: 睿宸 | Hits:

[Algorithm] CORDIC-example-code

Description: CORDIC Actel example VHDL code
Platform: | Size: 1373184 | Author: homan | Hits:

[WEB Code] aite_fileadmin_v1.0

Description: 爱特PHP版全能网站文件管理专家，支持文件批量复制、批量上传、批量网址获娶批量压缩文件，批量移动文件和建立目录，单文件Gzip,Bzip2，创建文件复件支持，任意文件下载支持，文件效验MD5,Sha1，权限设置，硬盘使用情况查看，远程FTP文件上传操作等。 　　注意：程序运行于PHP5+ SESSION环境，首次使用提示创建帐号密码，修改密码直接编辑admin.php文件。-Actel website PHP version Almighty document management experts to support bulk copy files, batch upload, batch URL was married bulk compressed files, move files and create directories batch, single-file Gzip, Bzip2, create a file copy support, support to download any file, document efficacy MD5, Sha1, permission settings, view disk usage, remote FTP file upload operation. Note: The program runs on PHP5+ SESSION environment, the first use of prompts to create a username and password, change the password directly edit the admin.php file.
Platform: | Size: 47104 | Author: spudn81 | Hits:
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