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[Embeded-SCM Develop] spaceguide_PIB200904

Description: 来自业界著名军品厂商ACTEL的军品选型手册-ACTEL SPACE GUIDE PB
Platform: | Size: 1014784 | Author: 贾存玉 | Hits:

[VHDL-FPGA-Verilog] Libra_ps2key_lcd

Description: 用Verilog语言实现的PS2小键盘输入和1602 LCD显示的功能。无需修改，已经调试通过了。直接可以当成一个模块用于FPGA/CPLD系统开发过程。这个代码是我在Libra环境下开发Actel FPGA时写的。-Verilog language using the PS2 keyboard and a small 1602 LCD display features. No changes have been adopted debugging. Directly as a module for the FPGA/CPLD system development process. This code is my development environment in Libra when written in Actel FPGA.
Platform: | Size: 6144 | Author: 赵二虎 | Hits:

[VHDL-FPGA-Verilog] A3P030_Comparator

Description: Actel的FPGA A3P030 做的数字比较起的源码-Actel FPGA A3P030 Comparator
Platform: | Size: 111616 | Author: 宋吉波 | Hits:

[SCM] uart

Description: 本程序的功能是实现串口通信，采用232传输协议，编码方式为8B/10B转换，即一位起始位，8位数据位，一位停止位，在actel Fusion系列开发板上得到验证，具有很强的通用性。本程序的编程语言为Verilog.-This procedure is to achieve the functions of serial communication, the transfer protocol is 232.The encoding protocol is 8B/10B , that is, a start bit, 8 data bits, one stop bit.It has been verified in the development-board of actel Fusion Series , and is highly versatile.The programming language used in this module is verilog.
Platform: | Size: 2048 | Author: 何斌 | Hits:

[Documents] Sch

Description: 常用的sch元件库，里面包含有最常用的库。以方便大家对sch的使用-Sch common library, which contains the most commonly used database. In order to facilitate the use of sch
Platform: | Size: 4840448 | Author: 胡杨彬 | Hits:

[VHDL-FPGA-Verilog] clock

Description: 用verilog实现的数字钟，已经在ACTEL公司的A3P030的开发板上成功运行-Digital clock with Verilog , successfully ran on the board of ACTEL A3P030
Platform: | Size: 4096 | Author: 萧月 | Hits:

[VHDL-FPGA-Verilog] UART_LCD

Description: 基于Actel的Fusion系列FPGA的UART串口，带FIFO-Based on Actel s Fusion Series of FPGA serial UART with FIFO
Platform: | Size: 8192 | Author: 戚海峰 | Hits:

[VHDL-FPGA-Verilog] JDL12864LCD

Description: 基于Actel A3P030 FPGA，液晶采用JDL12864串行接口，时钟48MHz-Based on Actel A3P030 FPGA, LCD using JDL12864 serial interface, clock 48MHz
Platform: | Size: 4096 | Author: songxin | Hits:

[VHDL-FPGA-Verilog] 111

Description: Verilog语言编写的循环彩灯控制器这个程序我已经在Actel板上烧过了，没问题。如果还有什么问题应该是你的板不同或者工具不同，我是在libero_8.5上做的 -VeriloG HDL IS VEVRY USEFUL
Platform: | Size: 4096 | Author: xinran | Hits:

[Other] grlib-gpl-1.0.21-b3848.tar

Description:
Platform: | Size: 17900544 | Author: Gopi | Hits:

[Other] TemperatureMonitor_lab

Description: 实现温度的实时的检测，使用Verilog语言，适用于actel公司的FPGA-To achieve real-time temperature detection, the use of Verilog language, the company' s FPGA for actel
Platform: | Size: 1906688 | Author: 王宏 | Hits:

[VHDL-FPGA-Verilog] hdl

Description: ACTEL FPGA 6位数码管计数999999，Verilog描述-ACTEL FPGA 6 bits digital tube count 999999, Verilog description
Platform: | Size: 3072 | Author: gouyouwen | Hits:

[VHDL-FPGA-Verilog] Compare_4bit_74hc85

Description: ACTEL FPGA 74HC85实例演示，Verilog描述-ACTEL FPGA 74HC85 examples demonstrate, Verilog description
Platform: | Size: 16384 | Author: gouyouwen | Hits:

[VHDL-FPGA-Verilog] ADC

Description: ACTEL FUSION STARTKIT FPGA 开发板例程，实现16通道的adc转换控制 adc精度12位 / 10位可调 -ACTEL FUSION STARTKIT FPGA development board routines, to achieve 16-channel control of adc adc conversion precision 12-bit/10 adjustable
Platform: | Size: 488448 | Author: zhangyujun | Hits:

[VHDL-FPGA-Verilog] 74hc4017

Description: 实现的是扭环形十进制计数器，用verilog HDL 语言，在Actel公司提供的LiberoFPGA开发环境下实现，代码经过验证，可在ModelSim中仿真 -Ring is twisted to achieve a decimal counter, using verilog HDL language, Actel offers the LiberoFPGA development environment, the code is validated, the simulation in the ModelSim
Platform: | Size: 484352 | Author: kmao | Hits:

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[Embeded-SCM Develop] spaceguide_PIB200904

[VHDL-FPGA-Verilog] Libra_ps2key_lcd

[VHDL-FPGA-Verilog] A3P030_Comparator

[SCM] uart

[Documents] Sch

[VHDL-FPGA-Verilog] clock

[VHDL-FPGA-Verilog] UART_LCD

[VHDL-FPGA-Verilog] JDL12864LCD

[VHDL-FPGA-Verilog] 111

[Other] grlib-gpl-1.0.21-b3848.tar

[Other] TemperatureMonitor_lab

[VHDL-FPGA-Verilog] hdl

[VHDL-FPGA-Verilog] Compare_4bit_74hc85

[VHDL-FPGA-Verilog] ADC

[VHDL-FPGA-Verilog] 74hc4017

[VHDL-FPGA-Verilog] hdl

[VHDL-FPGA-Verilog] FPGA_BUS

[VHDL-FPGA-Verilog] DFF

[VHDL-FPGA-Verilog] FlashLock_test

[VHDL-FPGA-Verilog] Actel_get_started_fusion

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