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[Other] SH6883 DL : 0: The SH6883 is designed for high performance Low-speed USB devices. It contains an 8051 micro-controller, Low-Speed USB SIE, Transceiver and data FIFO, build-in 3.3V regulator, on-chip 8K bytes Mask ROM and internal 256 bytes data RAM, Time capture circuit, Base timer, programmable Watch-dog timer and Wake-up timer, 37 Selectable GPIO (on 48-pin LQFP package), support multiple type LED driving capability for different application, build-in internal 32KHz oscillator, POR and LVR circuit saving your external components cost
Date : 2018-08-11 Size : 2.06mb User : simoon
[Other] SH68F093 DL : 0: SH68F093, an 8-bit micro-controller, is designed for the high-performance and low-power RF mouse application. The micro- controller contains on-chip flash-type program 16K bytes ROM, internal 512 bytes RAM, two 8-bit base timers, a wake-up timer, a watch-dog timer, a DC-DC converter, a 1.8V regulator for μP core, built-in 8MHz RC resonator, POR/LVR reset, resume reset, programmable voltage comparator, and master/slave SPI interface.
Date : 2018-08-11 Size : 536.59kb User : simoon
[Other] STM32MP151A数据手册 DL : 0: The STM32MP151A/D devices are based on the high-performance Arm® Cortex®-A7 32-bit RISC core operating at up to 800 MHz. The Cortex-A7 processor includes a 32-Kbyte L1 instruction cache, a 32-Kbyte L1 data cache and a 256-Kbyte level2 cache. The Cortex-A7 processor is a very energy-efficient application processor designed to provide rich performance in high-end wearables, and other low-power embedded and consumer applications. It provides up to 20% more single thread performance than the Cortex-A5 and provides similar performance than the Cortex-A9.
Date : 2020-12-14 Size : 1.7mb User : tonado_1
[Other] APPLICATION OF SVM IN DTC OF PMSM DL : 0: APPLICATION OF SPACE VECTOR MODULATION IN DTC OF PMSM
Date : 2021-01-03 Size : 216.05kb User : bens082002
[Other] Load Shedding Application within a Microgrid to Assure Its Dynamic Performance during Its Transition to the Islanded Mod DL : 0: This article presents the simulation results and analysis related to the response of the generators within a microgrid to- wards an accidental overload condition that will require some load shedding action. A microgrid overload can occur due to various reasons ranging from poor load schedule,
Date : 2021-08-01 Size : 782.33kb User : fellahi79
[Other] Comparative study of FFA architectures using different multiplier and adder topologies DL : 0: Parallel FIR filter is the prime block of many modern communication application such as MIMO, multi-point transceivers etc. But hardware replication problem of parallel techniques make the system more bulky and costly. Fast FIR algorithm (FFA) gives the best alternative to traditional parallel techniques. In this paper, FFA based FIR structures with different topologies of multiplier and adder are implemented. To optimize design different multiplication technique like add and shift method, Vedic multiplier and booth multiplier are used for computation. Various adders such as carry select adder, carry save adder and Han-Carlson adder are analyzed for improved performance of the FFA structure. The basic objective is to investigate the performance of these designs for the tradeoffs between area, delay and power dissipation. Comparative study is carried out among conventional and different proposed designs. The advantage of presented work is that; based on the constraints, one can select the suitable design for specific application. It also fulfils the literature gap of critical analysis of FPGA implementation of FFA architecture using different multiplier and adder topologies. Xilinx Vivado HLS tool is used to implement the proposed designs in VHDL.
Date : 2021-10-05 Size : 1.07mb User : nalevihtkas