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[Program doc] Multisim DL : 0: Multisim使用说明书本手册针对进行一般模拟电路仿真的MultisimV7用户，概括了MultisimV7单机教学版的安装和主要功能，指导读者逐步地建立一个基本电路，并进行仿真、分析。本手册所描述的大多数功能，各种版本的MultisimV7都具备。-Multisim use of the manual specification against the general analog circuit simulation Multisi mV7 users, summarized the teaching MULTISIMV7 single version of the installation and main function, readers gradually establishing a basic circuit simulation and analysis. The manual describes the majority of functions, all versions of the MULTISIMV7 possess.
Date : 2025-12-16 Size : 1.07mb User : 张厂
[Program doc] chengfaqi(xuniyiqi) DL : 0: 一个以LABVIEW环境开发的乘法器程序后面板和前面板-LABVIEW environment for the development of a multiplier after the panel and front panel
Date : 2025-12-16 Size : 63kb User : beny
[Program doc] Parallel-optimization DL : 0: 介绍用于光纤通信的速率为2.5 Gb/s的高速RS(255,239)译码器设计。对输入信号中可能出现的超出译码器纠错能力的误码可进行检测判断,保证了误码不扩散。对译码器中大量使用的有限域乘法器进行了优化设计,尤其对并行钱氏搜索电路中的乘法器采用了按组优化设计方法,与直接实现方法相比,复杂度降低了45 -For optical fiber is introduced at a rate of 2.5 Gb/s (255239) of the high speed RS decoder design. Of the input signal of possible super Out of the error correction decoder ability can detect judgment, to ensure the error non-proliferation. To use a lot of decoder limited domain on time-multiplier, the optimization design, especially for parallel once in the circuit on time-multiplier search by the group of optimization design method, and the direct method, compared to 45 lower complexity
Date : 2025-12-16 Size : 80kb User : 孟君
[Program doc] ReedSolomon-decode-new-circuit DL : 0: 用于RS码译码的两种新电路:普通基“比特串行序列乘法电路”和“比特串行乘法累加电路”,基本上以m个与门代替了两个任意元素相乘的复杂乘法器,使译码电路大大简化.作为一个应用实例,详细阐明了用它们构造的RS码纠删/纠错译码各步电路. -Used for RS code of decoding two new circuit: common base "bit serial sequence multiplication circuit" and "bit serial multiplication accumulate circuit", basically to m a door and instead of the two elements multiplication of any complex on time-multiplier, make the decoding circuit greatly simplified. As an application example, a detailed clarify the structure of the RS code with them when the delete/error correction decode each step circuit.
Date : 2025-12-16 Size : 42kb User : 孟君
[Program doc] Phase-and-Frequency-Detector DL : 0: 针对锁频锁相器( Phase and Frequency Detector, PFD) 应用于低信噪比、大频偏的条件, 通过理论分析和仿真验证阐述了窗口类型对系统频偏捕获速度、范围、噪声门限及相位噪声抖动的影响机理. 推导出等效相位噪声功率谱密度的表达式. 证明了大窗口具有更低的噪声门限和更小的稳态相位抖动, 但捕获速度较慢. 为了提高捕获速度, 对鉴相器输出值取极性运算得到改进的PFD 算法. 新算法不仅能增加鉴相增益提高捕获速度还可以减少等效噪声功率谱密度降低相位抖动同时新算法不需要乘法器便于硬件实现. 最后新算法的性能通过仿真得到了验证.-For frequency-locking phase-locked (Phase and the Frequency Detector PFD) conditions applied to the low signal to noise ratio, frequency offset, through theoretical analysis and simulation described the capture speed of the window type, the system frequency deviation, range, noise threshold and phase noise jitter mechanism. equivalent phase noise power spectral density expression is derived to prove the large windows with a lower noise threshold and the steady-state phase jitter, but to capture slow in order to improve the capture speed, The phase detector output value to take the polarity operator improved PFD algorithm. new algorithm not only can increase the phase gain to improve the capture speed can also reduce the equivalent noise power spectral density to reduce the phase jitter new algorithm does not require a multiplier to facilitate hardware implementation performance of the last new algorithm has been verified through simulation.
Date : 2025-12-16 Size : 456kb User : jing
[Program doc] DA-500-600 DL : 0: Distributed arithmetic used for multiplier-less FIR filter implementation to reduce the computational complexity.
Date : 2025-12-16 Size : 91kb User : sakhi
[Program doc] lagelangrichengzifa DL : 0: 用拉格朗日乘子法解有约束优化问题的matlab程序。-Lagrange multiplier method for solving constrained optimization problems matlab program.
Date : 2025-12-16 Size : 88kb User : liqi
[Program doc] FUAD DL : 0: Multi SSH. This software can open multiplier ssh. This software using bitvise tunnelier.
Date : 2025-12-16 Size : 1kb User : Den Bagus
[Program doc] multiplier DL : 0: It decsribes on 16*16 multiplier baced on booth algorithm. it may be useful to all.
Date : 2025-12-16 Size : 49kb User : Arunkumar
[Program doc] Performance-of-an-embedded-optical-vector-matrix- DL : 0: An embedded architecture of optical vector matrix multiplier (OVMM) is presented. The embedded architecture is aimed at optimising the data flow of vector matrix multiplier (VMM) to promote its performance. Data dependence is discussed when the OVMM is connected to a cluster system. A simulator is built to analyse the performance according to the architecture. According to the simulation, Amdahl’s law is used to analyse the hybrid opto–electronic system. It is found that the electronic part and its interaction with optical part form the bottleneck of system.
Date : 2025-12-16 Size : 454kb User : sf
[Program doc] Planar-integrated-optical-vector-matrix-multiplie DL : 0: We present the design of a planar-integrated optoelectronic vector-matrix multiplier. The inherent parallel-processing potential is fully exploited by optical implementation of multiplications and summations. Planar integration makes the free-space optical system compatible with electronic VLSI technologies. It is composed of phase-only diffractive optical elements, which implement lens and multiple-beam-splitter functions. A demonstrator version of the optical system for a matrix of size 10 3 10 was fabricated on quartz glass by means of multimask lithography and reactive ion etching. It shows low cross talk and good uniformity of the signals.
Date : 2025-12-16 Size : 2.57mb User : sf
[Program doc] latch DL : 0: Abstract—Power is becoming a precious resource in modern VLSI design, even more so than area. This paper proposes a novel architecture for modular, scalable &reusable hybrid constant co-efficient multiplier (KCM) circuit. Comparison is made between of kcm and multiplier. The implementation results show a significant improvement in performance in terms of area, power & timing. In This paper, we propose to design an 8-point FFT using kcm instead of complex multiplier and multiplier. Here our goal is to implement Radix-2 8-point FFT in hardware using hardware language (verilog) here time constraint is measured with the help of Xilinx FPGA (Field Programmable Gate Array).
Date : 2025-12-16 Size : 547kb User : Bahu
[Program doc] matlab DL : 0: Increase the simulation time in the script, the simulated and theoretical results should converge • Use a pulse shaping filter at the transmitter • At the receiver, precede the discrete-time integrator with a multiplier by a replica of the transmitted pulse to construct a correlator-Increase the simulation time in the script, the simulated and theoretical results should converge • Use a pulse shaping filter at the transmitter • At the receiver, precede the discrete-time integrator with a multiplier by a replica of the transmitted pulse to construct a correlator
Date : 2025-12-16 Size : 106kb User : tag