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[Software Engineering] Booth_mutipler DL : 0: 布思基四乘法器实现,很好用,快来看,希望对大家有所帮助.-Busaiji four multiplier, useful, Come see, we want to help.
Date : 2008-10-13 Size : 1.42mb User : fghgh
[Software Engineering] The Linux Kernel API DL : 0: The Linux Kernel API是学习linux编程必备资料，学会API那么做软件开发就会事半功倍。-The Linux Kernel API is learning linux programming required information, and learn to do it API software development will multiplier.
Date : 2025-12-16 Size : 168kb User : yxl
[Software Engineering] Booth_mutipler DL : 0: 布思基四乘法器实现,很好用,快来看,希望对大家有所帮助.-Busaiji four multiplier, useful, Come see, we want to help.
Date : 2025-12-16 Size : 1.42mb User : fghgh
[Software Engineering] booth_multiplier DL : 0: Booth multiplier written in verilog
Date : 2025-12-16 Size : 1kb User : Udit
[Software Engineering] DDS-baseddesignofthesinusoidalsignalgenerator DL : 0: 本设计采用AT89552单片机，辅以必要的模拟电路，实现了一个基于直接数字频率合成技术(DDS)的正弦谊号发生器。设计中采用DDS芯片AD9850产生频率1KHZ~10MHZ范围内正弦波，采用功放AD811控制输出电压幅度，由单片机AT89S52控制调节步进频率1HZ。在此基础上，用模拟乘法器MC1496实现了正弦调制信号频率为1KHZ的模拟相度调制信号；用FPGA芯片产生二进制NRZ码,与AD9850结合实现相移键控PSK、幅移键控ASK、频移镇键FSK。-AT89552 the single-chip design, supplemented by the necessary analog circuits, based on the realization of a direct digital frequency synthesis (DDS) generator of sinusoidal No. Friends. The design of DDS chip AD9850 produced using 1KHZ ~ 10MHZ frequency range of sine wave, the AD811 control amplifier output voltage range of from single-chip AT89S52-conditioning step frequency control 1HZ. On this basis, the use of analog multiplier MC1496 has sinusoidal frequency modulation signal 1KHZ degree analog phase modulated signal generated by FPGA chip NRZ binary code, combined with the AD9850 to achieve phase shift keying PSK, ASK ASK, frequency Shift key town of FSK.
Date : 2025-12-16 Size : 204kb User : 何蓓
[Software Engineering] FPGA DL : 0: 基于FPGA数字乘法器的设计：数字乘法嚣是目前数字信号处理中运用最广泛的执行部件之一，本文设计了三种基于FPGA 的数字乘法器．分别是移位相加乘法嚣、加法器树乘法器和移位相加一加法嚣树混合乘法器。通过对三种方案的仿真综合以厦速度和面积的比较指出了混合乘法器是其中最佳的设计方案-FPGA-based digital multiplier design: the number of multiplicative noise is the use of digital signal processing in the most extensive one of the implementation of components, the paper design of the three types of FPGA-based digital multiplier. Shift sum are noise multiplication, adder tree multiplier and the sum of a displacement hybrid adder tree multiplier noise. Through the simulation of three options to building a comprehensive comparison of the speed and size that the multiplier is one of the best hybrid design
Date : 2025-12-16 Size : 144kb User : 南才北往
[Software Engineering] Coursework3 DL : 0: This paper illustrates an approach to design a 4 Quadrant multiplier circuit using BJT. A Quadrant multiplier basically consist of 2 matched differential pair units with BJTs. This principle was established by B.Gilbert in 1968 and the circuit is known as Gilbert’s cell. The operation of BJT and its working as a differential amplifier is explained in brief. Referring to the operation of the differential amplifier as a two quadrant multiplier, the operation of a four quadrant multiplier was analyzed. The basic Gilbert’s cell was simulated using PSpice and improvements were made to increase it linearity of the basic circuit.-This paper illustrates an approach to design a 4 Quadrant multiplier circuit using BJT. A Quadrant multiplier basically consist of 2 matched differential pair units with BJTs. This principle was established by B.Gilbert in 1968 and the circuit is known as Gilbert’s cell. The operation of BJT and its working as a differential amplifier is explained in brief. Referring to the operation of the differential amplifier as a two quadrant multiplier, the operation of a four quadrant multiplier was analyzed. The basic Gilbert’s cell was simulated using PSpice and improvements were made to increase it linearity of the basic circuit.
Date : 2025-12-16 Size : 136kb User : Rex
[Software Engineering] multi DL : 0: This a baugh-wooley multiplier verilog code-This is a baugh-wooley multiplier verilog code
Date : 2025-12-16 Size : 136kb User : lo-po
[Software Engineering] doublemult DL : 0: 设计了一个双精度浮点乘法器。该器件采用改进的BOO TH 算法产生部分积, 用阵列和树的混合结构实现对部分积的相加, 同时, 还采用了快速的四舍五入算法, 以提高乘法器的性能。把设计的乘法器分为4 级流水线, 用FPGA 进行了仿真验证, 结果正确并对FPGA 实现的时序结果进行了分析。-Designed a double-precision floating-point multiplier. The device uses an improved algorithm for BOO TH generate part of the plot, with a mixed array and a tree structure to achieve the sum of the partial product, while also using a fast rounding algorithm to improve the performance of multipliers. The design of the multiplier is divided into four lines, carried out a simulation using FPGA verification result is correct and FPGA timing to achieve the results analyzed.
Date : 2025-12-16 Size : 205kb User : terry
[Software Engineering] 4-bit-multiplier DL : 0: 4 bit multiplier program using shift and multiply
Date : 2025-12-16 Size : 2kb User : karthick
[Software Engineering] Multiplier DL : 0: 详细介绍了给予Verilog的乘法器设计过程。-Details the the multiplier given Verilog design process.
Date : 2025-12-16 Size : 305kb User : wind
[Software Engineering] wallacetree-16bit-multiplier DL : 0: 这是一种多功能的乘法器的设计思路,只要有了它,就能快速的解决乘法的问题,是卷积,求和,积分的好帮手.-This is a versatile multiplier design ideas, as long as you have it, you can quickly solve the problem of multiplication, convolution, summation, integral a good helper.
Date : 2025-12-16 Size : 105kb User : william
[Software Engineering] Multiplier DL : 0: 乘法器课程报告，华莱士树算法硬件实现，讲解详细-Multiplier course reports, Wallace tree algorithm implemented in hardware
Date : 2025-12-16 Size : 629kb User : yrh
[Software Engineering] the-Lagrange-multiplier-method- DL : 0: 约束优化算法：拉格朗日乘子法matlab程序-Constrained optimization algorithm: the Lagrange multiplier method and matlab program
Date : 2025-12-16 Size : 87kb User : 天
[Software Engineering] 4bit-multiplier DL : 0: four bit multiplier for testing softwares
Date : 2025-12-16 Size : 10kb User : sat
[Software Engineering] 4bit-booth-multiplier DL : 0: four bit booth multiplier for testing software
Date : 2025-12-16 Size : 10kb User : sat
[Software Engineering] Systolic-Multiplier DL : 0: Systolic multiplier is used to multiply 18-bit or more bit multiplication
Date : 2025-12-16 Size : 328kb User : KPSS
[Software Engineering] verilog-code-for-8bit-multiplier-using-vedic-algo DL : 0: The vedic multiplier is used perform 16 bit multiplication using urdhva tiryakbhyam sutra. this produces the results with high speed and utilizes low power which is most efficient for the real time processors.
Date : 2025-12-16 Size : 11kb User : naz
[Software Engineering] Design-of-Fixed-Width-Multiplier-Using-Baugh-Wool DL : 0: Design of Fixed-Width Multiplier Using Baugh-Wooley Algorithm
Date : 2025-12-16 Size : 537kb User : rkvrajan
[Software Engineering] multiplier DL : 0: structural multiplier
Date : 2025-12-16 Size : 1kb User : ali

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