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[MiddleWare] shiweichenfaqi DL : 0: maxplus做的四位乘法器，可下载仿真-The four maxplus multiplier, can be downloaded Simulation
Date : 2025-12-17 Size : 198kb User : 赵冉
[MiddleWare] fq_div DL : 0: pll 的64倍频锁相环技术用实现倍频从而达到对频率的分频-pll 64 multiplier PLL multiplier used to achieve so as to achieve the sub-band of frequencies
Date : 2025-12-17 Size : 2kb User : leo
[MiddleWare] multiplier DL : 0: a multiplier in vhdl, contains an alu and a control unit
Date : 2025-12-17 Size : 2kb User : george
[MiddleWare] multiplier_interface DL : 0: verilog 写的工程，是个基于流水线的乘法器-verilog write the works, is based on a pipelined multiplier
Date : 2025-12-17 Size : 3kb User : wns
[MiddleWare] MULTI4BIT DL : 0: 4位乘法器由于所使用的软件是ISE，没有LPM_ROM可以直接调用，所以此设计直接调用的乘法器的IP核来完成此功能，达到同样的效果。-Four multiplier
Date : 2025-12-17 Size : 65kb User : 李丽
[MiddleWare] Serial-parallel-multiplier-verilog-design DL : 0: Serial parallel multiplier verilog design source code
Date : 2025-12-17 Size : 27kb User : dorababugfree
[MiddleWare] pid_library_other_pic32 DL : 0: { interface } type TPIDController = record PID_Kp, PID_Ki, PID_Kd: real; PID_Integrated : real; PID_Prev_Input: real; PID_MinOutput, PID_MaxOutput: real; PID_First_Time, PID_Int_Improvement, PID_Diff_Improvement: boolean; PID_Prev_AbsError: real; end; procedure Init_PID(var Controller: TPIDController; Kp, Ki, Kd, MinOutput, MaxOutput: real); // Initialises the PID engine of "Controller" // Kp = the "proportional" error multiplier // Ki = the "integrated value" error multiplier // Kd = the "derivative" error multiplier // MinOutput = the minimal value the output value can have (should be < 0) // MaxOutput = the maximal value the output can have (should be > 0)
Date : 2025-12-17 Size : 181kb User : A.D
[MiddleWare] booth DL : 0: 基于booth算法的16位乘法器，通过减少部分积的运算次数提升速度。(The 16 bit multiplier based on the Booth algorithm improves the speed by reducing the number of arithmetic times of the partial product.)
Date : 2025-12-17 Size : 1kb User : JoincoreX