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[source in ebook] Visual C++. NET编程150例 DL : 0: >一书是学习C++.NET的最简洁方法，通过案例学习达到事半功倍的作用，非常不错的，想下就下吧！-lt; Lt; Visual C.NET programming 150 cases gt; Gt; A book is learning C.NET the most concise way, through case study and achieve a multiplier effect, very good, the next to the next!
Date : 2008-10-13 Size : 1.71mb User : 张永
[source in ebook] C_9 DL : 0: 100个经典vhdl编程实例，第1例带控制端口的加法器第2例无控制端口的加法器第3例乘法器第4例比较器第5例二路选择器第6例寄存器第7例移位寄存器第8例综合单元库第9例七值逻辑与基本数据类型第10例函数第11例七值逻辑线或分辨函数第12例转换函数第13例左移函数第14例七值逻辑程序包第15例四输入多路器...... -100 vhdl classical programming examples, No. 1 is the control port Adder first two cases of uncontrolled port Adder No. 3 Multiplier first four cases compared with the first five cases 2 Lu choice for the first six cases Register No. 7 cases shift register first eight cases consolidated for the first module nine cases seven-valued logic and basic data types No. 10 No. 11 cases function seven-valued logic function or defective Line No. 12 conversion functions No. 13 bits function section 14 cases 7 logic package No. 15 cases four multi-input devices ......
Date : 2025-12-17 Size : 329kb User :
[source in ebook] mult8_rtl DL : 0: 一个用VHDL语言编写的乘法器程序，望大家多多支持啊。-A language using VHDL multiplier process, hope everyone can support ah.
Date : 2025-12-17 Size : 2kb User : maomao
[source in ebook] design_of_GF_mul DL : 0: Date : 2025-12-17 Size : 2kb User : 石小磊
[source in ebook] butfly4 DL : 0: 基4-FFT蝶形单元实现，按照FPGA内部的乘法器功能编写的-4-FFT butterfly-based unit to achieve, in accordance with the internal FPGA multiplier feature prepared
Date : 2025-12-17 Size : 1kb User : 苏菲
[source in ebook] Windows_CE_Program_Code DL : 0: Windows CE程序设计随书源代码在学习的过程中，对照源程序，事半功倍-Programming Windows CE source code with the book in the learning process, the control source, a multiplier
Date : 2025-12-17 Size : 1.15mb User : hxh
[source in ebook] Chapter1-5 DL : 0: 第一章到第五章的代码本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相应的Testbench，所举实例具有很强的实用性和代表性，每个实例均给出了介绍、功能分析、程序代码和结果演示。-Chapter to Chapter V of the code in this book through more than 100 module instance, explain in detail the Verilog HDL programming language, the book is divided into 13 chapters, covering basic concepts VerilogHDL languages, modeling, synchronous design, asynchronous design, function authentication, etc. Examples include a variety of adder/counter, multiplier/divider, encoders/decoders, state machines, SPIMaster Controller, I2C Master controller, CAN ProtocolController, Memory modules, JPEG image compression module, encryption module, ATA controller, 8-bit RISC-CPU, etc. and the various instances of the corresponding module Testbench, The examples are highly practical and representation, each instance of it all gives the introduction, functional analysis, program code and results presentation.
Date : 2025-12-17 Size : 1.51mb User : xiao
[source in ebook] sanfenpin DL : 0: verilog 三分频分频器是FPGA设计中使用频率非常高的基本设计之一，尽管在目前大部分设计中，广泛使用芯片厂家集成的锁相环资源，如altera 的PLL，Xilinx的DLL.来进行时钟的分频，倍频以及相移。-verilog-third of the frequency divider is a FPGA design, very high frequency of use, one of the basic design, although most of the designs in the current widespread use of factory-integrated PLL chip resources, such as altera of the PLL, Xilinx' s DLL. to for the sub-clock frequency multiplier and phase shift.
Date : 2025-12-17 Size : 1kb User : 杨化冰
[source in ebook] ADSP_2126x_HRM DL : 0: High performance 32-bit/40-bit floating-point processor Code compatibility—at assembly level, uses the same instruction set as other SHARC DSPs Single-instruction multiple-data (SIMD) computational architecture— two 32-bit IEEE floating-point/32-bit fixed-point/ 40-bit extended precision floating-point computational units, each with a multiplier, ALU, shifter, and register file High bandwidth I/O—a parallel port, an SPI® port, six serial ports, a digital applications interface (DAI), and JTAG -High performance 32-bit/40-bit floating-point processor Code compatibility—at assembly level, uses the same instruction set as other SHARC DSPs Single-instruction multiple-data (SIMD) computational architecture— two 32-bit IEEE floating-point/32-bit fixed-point/ 40-bit extended precision floating-point computational units, each with a multiplier, ALU, shifter, and register file High bandwidth I/O—a parallel port, an SPI® port, six serial ports, a digital applications interface (DAI), and JTAG
Date : 2025-12-17 Size : 1.47mb User : ak
[source in ebook] MUTIPLIER_16 DL : 0: 16位乘法器的工程，用xilinx ISE设计，供初学者学习-16 multiplier works, the ISE xilinx design, for beginners to learn
Date : 2025-12-17 Size : 898kb User : 皇天
[source in ebook] signed_mult17b_addtree- DL : 0: 实现了17乘以17的带符号位的乘法器，采用流水结构，加法树结构-relize a multiplier by using add-tree and level archtiture.
Date : 2025-12-17 Size : 1kb User : 徐高伟
[source in ebook] PHR_multiplier_method DL : 0: 《最优化理论与方法》书籍中的乘子法的源程序，该书中的很多案例都用此方法试验过，本代码是一个小案例，将目标函数和约束函数按自己的需求换掉就能进行所期望的运算-" Optimization Theory and Methods" books multiplier method of the source, the book' s many cases are tested using this method, the code is a small case, the objective function and constraints to replace it according to their needs can perform the desired operation
Date : 2025-12-17 Size : 5kb User : wxq
[source in ebook] Chapter-2 DL : 0: 3.1加法树乘法器add_tree_mult设计实例, 3.2查找表乘法器lookup_mult设计实例. 3.3布尔乘法器booth_mult设计实例 3.4移位除法器shift_divider设计实例 -3.1 adder tree multiplier add_tree_mult design example, 3.2 lookup table multiplier lookup_mult design examples. 3.3 Design Example 3.4 Boolean multiplier booth_mult shift divider shift_divider design examples
Date : 2025-12-17 Size : 212kb User : shixiaodong
[source in ebook] Chapter-3 DL : 0: 3.1加法树乘法器add_tree_mult设计实例 3.2查找表乘法器lookup_mult设计实例 3.3布尔乘法器booth_mult设计实例 3.4移位除法器shift_divider设计实例-3.1 adder tree multiplier add_tree_mult design example 3.2 multiplier lookup_mult lookup table design example 3.3 Design Example 3.4 Boolean multiplier booth_mult shift divider shift_divider design examples
Date : 2025-12-17 Size : 453kb User : shixiaodong
[source in ebook] Chapter-5 DL : 0: 5.2　16位乘法器状态机实现 5.3　交通控制灯控制设计　 5.4　PCI总线目标接口状态机设计-5.2 16 5.3 multiplier state machine traffic light control design 5.4 PCI bus target interface state machine design
Date : 2025-12-17 Size : 366kb User : shixiaodong
[source in ebook] Proj2_final DL : 0: 2 4 8级流水线乘法器以及除法器包括makefile 和 tcl 比较详细-248 stage pipeline multiplier and divider includes more detailed makefile and tcl
Date : 2025-12-17 Size : 24kb User : 曹远航
[source in ebook] RSAjiami DL : 0: RSA算法中大数幂乘，大素数判断，求逆元，大整数乘法-RSA algorithm in the large number of power multiplier, large prime judgments, seeking inverse yuan, large integer multiplication
Date : 2025-12-17 Size : 908kb User : 罗毅