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[MPI] Cache_FIFO DL : 0: 模拟内存高速缓存技术C源码，主要是FIFO形式。-simulated high-speed cache memory technology C source code, is the main form of FIFO.
Date : 2025-12-22 Size : 2kb User : 夏军
[MPI] fifo_ver_131 DL : 0: fifo verilog hdl 源程序-fifo verilog hdl source
Date : 2025-12-22 Size : 20kb User : zlw
[MPI] fifo_vhd_131 DL : 0: fifo vhdl源程序-fifo vhdl source
Date : 2025-12-22 Size : 15kb User : zlw
[MPI] v2_fifo_vhd_258 DL : 0: 这是一个基于xilinx ISE9.1的一个历程，包含两个FIFO代码，第一个FIFO读写用同一个时钟，第二个FIFO读写用不同的时钟。-This is a xilinx ISE9.1 based on a course code consists of two FIFO, the first FIFO read and write using the same clock, the second FIFO read and write with a different clock.
Date : 2025-12-22 Size : 90kb User : muerqing
[MPI] zhongduan DL : 0: 根据所给的内存块数以及不同作业（进程）占用的时间片的不同，分别以FIFO或者LRU算法得到进程缺页中断情况-list the pause stuation in two differant ways...such as FIFO,LRu.
Date : 2025-12-22 Size : 1kb User : 王亚军
[MPI] uartfifo DL : 0: 以Proasic3 Start kit开发板为平台，介绍了FIFO的基本功能。-ProASIC3 Start Kit development board as a platform to introduce the basic functions of the FIFO.
Date : 2025-12-22 Size : 885kb User : 章泽良
[MPI] SDRAM_FPGA DL : 0: 这个是SDRAM的控制程序，包括包括UART和FIFO模块，适合FPGA开发人员看，也适合初学者学习。-This is the SDRAM control procedures, including including UART and FIFO module, suitable for FPGA developers look, but also suitable for beginners to learn.
Date : 2025-12-22 Size : 2.82mb User : zhangquanling
[MPI] segment-page DL : 0: 段页式虚拟设计管理用于操作系统课程设计作业，可支持LRU和FIFO访问-Virtual Design Management section page
Date : 2025-12-22 Size : 4kb User : yufan
[MPI] FIFO DL : 0: FIFO读写操作，quartusII VHDL IP FPGA-FIFO VHDL IP FPGA
Date : 2025-12-22 Size : 98kb User : eclipseds5