ProASIC3 Start Kit development board as a platform to introduce the basic functions of the FIFO.

uartfifo\designer\impl1\designer.log
........\........\.....\FIFO_top.adb
........\........\.....\FIFO_top.ide_des
........\........\.....\FIFO_top.tcl
........\........\.....\FIFO_top_2.adb
........\........\.....\...........dtf\verify.log
........\........\.....\FIFO_top_2.ide_des
........\........\.....\FIFO_top_2.pdb
........\........\.....\FIFO_top_2.pdb.depends
........\........\.....\FIFO_top_2_ba.sdf
........\........\.....\FIFO_top_2_ba.v
........\........\.....\...........fp\$$FlashPro_09003.L$$
........\........\.....\.............\FIFO_top_2.log
........\........\.....\.............\FIFO_top_2.pro
........\........\.....\.............\projectData\FIFO_top_2.pdb
........\........\.....\syn_fifo.adb
........\........\.....\syn_fifo.ide_des
........\........\.....\syn_fifo.tcl
........\hdl\ctrl_FIFO.v
........\...\FIFO_top.v
........\...\rec.v
........\...\send.v
........\simulation\modelsim.ini
........\..........\modelsim.ini.sav
........\..........\modelsim.log
........\..........\presynth\ctrl_@f@i@f@o\verilog.psm
........\..........\........\.............\_primary.dat
........\..........\........\.............\_primary.dbs
........\..........\........\.............\_primary.vhd
........\..........\........\_info
........\..........\run.do
........\..........\vsim.wlf
........\.martgen\smartgen.aws
........\........\.yn_fifo\syn_fifo.cxf
........\........\........\syn_fifo.gen
........\........\........\syn_fifo.log
........\........\........\syn_fifo.v
........\........\........1\syn_fifo1.cxf
........\........\.........\syn_fifo1.gen
........\........\.........\syn_fifo1.log
........\........\.........\syn_fifo1.v
........\........\syn_fifo1_work.ixf
........\........\syn_fifo_work.ixf
........\.ynthesis\backup\FIFO_top.srr
........\.........\......\FIFO_top_2.srr
........\.........\ctrl_FIFO.areasrr
........\.........\ctrl_FIFO.htm
........\.........\ctrl_FIFO.map
........\.........\ctrl_FIFO.sap
........\.........\ctrl_FIFO.so
........\.........\ctrl_FIFO.srd
........\.........\ctrl_FIFO.srr
........\.........\ctrl_FIFO_syn.prj
........\.........\FIFO_top.areasrr
........\.........\FIFO_top.htm
........\.........\FIFO_top.map
........\.........\FIFO_top.sap
........\.........\FIFO_top.so
........\.........\FIFO_top.srd
........\.........\FIFO_top.srr
........\.........\FIFO_top_1.areasrr
........\.........\FIFO_top_1.htm
........\.........\FIFO_top_1.map
........\.........\FIFO_top_1.sap
........\.........\FIFO_top_1.so
........\.........\FIFO_top_1.srd
........\.........\FIFO_top_1.srr
........\.........\FIFO_top_2.areasrr
........\.........\FIFO_top_2.edn
........\.........\FIFO_top_2.fse
........\.........\FIFO_top_2.htm
........\.........\FIFO_top_2.map
........\.........\FIFO_top_2.sap
........\.........\FIFO_top_2.sdf
........\.........\FIFO_top_2.so
........\.........\FIFO_top_2.srd
........\.........\FIFO_top_2.srm
........\.........\FIFO_top_2.srr
........\.........\FIFO_top_2.srs
........\.........\FIFO_top_2.tlg
........\.........\FIFO_top_2_sdc.sdc
........\.........\FIFO_top_syn.prj
........\.........\run_options.txt
........\.........\stdout.log
........\.........\.yntmp\ctrl_FIFO.msg
........\.........\......\ctrl_FIFO.plg
........\.........\......\ctrl_FIFO_flink.htm
........\.........\......\ctrl_FIFO_srr.htm
........\.........\......\ctrl_FIFO_toc.htm
........\.........\......\FIFO_top.msg
........\.........\......\FIFO_top.plg
........\.........\......\FIFO_top_1.msg
........\.........\......\FIFO_top_1.plg
........\.........\......\FIFO_top_1_flink.htm
........\.........\......\FIFO_top_1_srr.htm
........\.........\......\FIFO_top_1_toc.htm
........\.........\......\FIFO_top_2.msg
........\.........\......\FIFO_top_2.plg
........\.........\......\FIFO_top_2_flink.htm
........\.........\......\FIFO_top_2_srr.htm

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