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[VHDL-FPGA-Verilog] cache DL : 0: 原创VERILOG HDL 实现CACHE的操作，有需要请下载-original verilog HDL achieve CACHE operation, the need to download
Date : 2025-12-25 Size : 4kb User : MingCheng
[VHDL-FPGA-Verilog] VHDLserial DL : 0: UART参考设计带缓存用于Xinlix用于FPGA-UART reference design with cache for Xinlix for FPGA
Date : 2025-12-25 Size : 273kb User : sd
[VHDL-FPGA-Verilog] pingpang DL : 0: 实现乒乓缓存，用verilog语言编写！-Realize cache ping-pong, using Verilog language!
Date : 2025-12-25 Size : 162kb User : zhl
[VHDL-FPGA-Verilog] vga_card DL : 0: VGA模块的VHDL代码和软件驱动，可作为外设挂接在Avalon总线上。用一块SRAM作为显存，双缓存切换模式。-VGA module VHDL code and software drivers can be articulated as a peripheral bus in Avalon. As with a piece of SRAM memory, dual-mode cache switching.
Date : 2025-12-25 Size : 6kb User : ctqy
[VHDL-FPGA-Verilog] pingpang DL : 0: 关于乒乓操作的，对于数据缓存有很大的用处-On the ping-pong operation of data cache for the great usefulness of
Date : 2025-12-25 Size : 163kb User : 敬亮
[VHDL-FPGA-Verilog] mips1 DL : 0: Verilog MIPS design. I found it somewhere on Internet and it is working :-Verilog MIPS design. I found it somewhere on Internet and it is working :))))
Date : 2025-12-25 Size : 18kb User : Asparuh Grigorov
[VHDL-FPGA-Verilog] cameralink DL : 0: 由于目前基于CameraLink接口的各种相机都不能直接显示，因此本文基于Xilinx公司的Spartan 3系列FPGAXC3S1000-6FG456I设计了一套实时显示系统，该系统可以在不通过系统机的情况下，完成对相机CameraLink信号的接收、缓存、读取并显示系统采用两片SDRAM作为帧缓存，将输入的CameraLink信号转换成帧频为75Hz，分辨率为1 024×768的XGA格式信号，并采用ADV7123JST芯片实现数模转换，将芯片输出的信号送到VGA接口，通过VGA显示器显示出来-As the CameraLink interface is currently based on a variety of cameras can not directly display, this article based on Xilinx' s Spartan 3 series FPGAXC3S1000-6FG456I designed a set of real-time display system, the system can be achieved without machine case through the system to complete the CameraLink cameras signal reception, cache, read and display systems use two SDRAM frame buffer as the input signals into the CameraLink frame rate of 75Hz, a resolution of 1 024 × 768 for XGA format signal, and using ADV7123JST chip digital-analog conversion, the chip output signal to the VGA port, through the VGA display monitor
Date : 2025-12-25 Size : 13kb User : lilei
[VHDL-FPGA-Verilog] dCACHE DL : 0: Vhdl写的数据cache,根据Verilog程序改编-Vhdl write data cache
Date : 2025-12-25 Size : 10kb User : 赵元杰
[VHDL-FPGA-Verilog] iCACHE DL : 0: 用VHDL写的数据cache，基于Verilog版本改编过来-To use VHDL to write the data cache, based on the Verilog version of the adaptation over
Date : 2025-12-25 Size : 7kb User : 赵元杰
[VHDL-FPGA-Verilog] CIC_Moore DL : 1: It is a complete project of Cache Interface Controller programmed in VHDL using the logic of Moore State Machine
Date : 2025-12-25 Size : 353kb User : Mr J
[VHDL-FPGA-Verilog] PIPE_LINING_CPU_TEAM_24 DL : 0: 采用Quatus II编译环境，使用Verilog HDL语言编写实现了五段流水线CPU。能够完成以下二十二条指令（均不考虑虚拟地址和Cache，并且默认为小端方式）： add rd,rs,rt addu rd,rs,rt addi rt,rs,imm addiu rt,rs,imm sub rd,rs,rt subu rd,rs,rt nor rd,rs,rt xori rt,rs,imm clo rd,rs clz rd,rs slt rd,rs,rt sltu rd,rs,rt slti rt,rs,imm sltiu rt,rs,imm sllv rd,rt,rs sra rd,rt,shamt blez rs,imm j target lwl rt,offset(base) lwl rt,offset(base) lw rt,imm(rs) sw rt,imm(rs) 在本设计中，采取非常良好的模块化编程风格，共分十三个主要模块PIPE_LINING_CPU_TEAM_24.v为顶层实体文件，对应为PIPE_LINING_CPU_TEAM_24模块作为顶层实体模块，如下： ifetch.v、regdec.v、exec.v、mem.v、wr.v分别实现五个流水段； cpuctr.v用于产生CPU控制信号； ALU.v用于对操作数进行相应指令的运算并输出结果； DM.v数据存储器 IM.v指令存储器 datareg.v数据寄存器堆 extender.v位扩展 yiwei_32bits.v 实现32位四种移位方式的移位器在顶层实体中，调用ifetch.v、regdec.v、exec.v、mem.v、wr.v这五个模块就实现了流水线CPU。顶层模块的结构清晰明了。对于学习verilog编程非常有用- Quatus II compiled by the environment, using Verilog HDL language to achieve a five-stage pipeline CPU. To complete the following 22 commands (not considering the virtual address and Cache, and the default mode for the small end): add rd, rs, rt addu rd, rs, rt addi rt, rs, imm addiu rt, rs, imm sub rd, rs, rt subu rd, rs, rt nor rd, rs, rt xori rt, rs, imm clo rd, rs clz rd, rs slt rd, rs, rt sltu rd, rs, rt slti rt, rs, imm sltiu rt, rs, imm sllv rd, rt, rs sra rd, rt, shamt blez rs, imm j target lwl rt, offset (base) lwl rt, offset (base) lw rt, imm (rs) sw rt, imm (rs) In this design, take a very good modular programming style, is divided into 13 main modules PIPE_LINING_CPU_TEAM_24.v for the top-level entity file, the corresponding module as a top-level entity for the PIPE_LINING_CPU_TEAM_24 modules, as follows: ifetch.v, regdec.v, exec.v, mem.v, wr.v water were to achieve the five paragraph cpuctr.v used to generate CPU control signal ALU.v accordingly
Date : 2025-12-25 Size : 4.72mb User : 石
[VHDL-FPGA-Verilog] cache DL : 0: 缓存器 cache verilog 欢迎下载偶-cache verilog
Date : 2025-12-25 Size : 5kb User : yzhang
[VHDL-FPGA-Verilog] vhdl DL : 0: 该系统通过顶层模块，调用7底层模块实现。7大模块底层模块为：理想信源数据接收模块，理想信源数据缓存模块，LAPS成帧模块，加扰并发送LAPS帧模块，接收LAPS帧并解扰模块，接收LAPS帧数据缓存模块，解帧并发送数据给理想信源模块。另，还有一个fifo模块，以便两个缓存模块调用。-The system top-level module, called 7, the bottom module. Bottom-7 module module: the ideal source of data receiver module, an ideal source of data cache module, LAPS framing module, scrambling and send LAPS frame module, receiving and descrambling module LAPS frame, receive LAPS frame data buffer module, solution frame and sending data to a good source module. The other, there is a fifo module to call the two cache modules.
Date : 2025-12-25 Size : 6kb User : mao
[VHDL-FPGA-Verilog] cache DL : 1: 本文给出了一个cache的所有源代码，存为txt格式的压缩包-this is a code of a cache
Date : 2025-12-25 Size : 1kb User : 张的的
[VHDL-FPGA-Verilog] fm25h20 DL : 0: spi接口，DSP发送数据，FPGA缓存起来，然后通过spi口写进fm25h20芯片里面-Spi interface, DSP send data, FPGA, and then through the spi cache up mouth written into fm25h20 chip inside
Date : 2025-12-25 Size : 5kb User : lg
[VHDL-FPGA-Verilog] fifo DL : 0: 用vhdl语言实现对八位数据进行缓存的控制-With VHDL language implementation to eight of the data cache of control
Date : 2025-12-25 Size : 511kb User : avir
[VHDL-FPGA-Verilog] CPUwithout-cache DL : 0: 5级流水无cache,CPU实验，是学习VHDL的好资料，对于了解CPU很有帮助！-5-stage pipeline without cache, CPU test, is learning VHDL good information, very helpful for understanding the CPU!
Date : 2025-12-25 Size : 461kb User : 张洋
[VHDL-FPGA-Verilog] PipelineCPU DL : 0: 用Verilog HDL语言或VHDL语言来编写，实现多周期CPU设计。能够完成以下二十二条指令。（均不考虑虚拟地址和Cache，并且默认为大端方式）： add rd, rs, rt addu rd, rs, rt addi rt, rs, imm addiu rt, rs, imm sub rd, rs, rt subu rd, rs, rt nor rd, rs, rt xori rt, rs, imm clo clz slt rd, rs, rt sltu rd, rs, rt slti rt, rs, imm sltiu rt, rs, imm sllv rd，rt，rs sra rd，rt，shamt blez rs, imm j target lwl rt，offset（base） lwr rt，offset（base） lw rt，imm（rs） sw rt，imm（rs） -Written in Verilog HDL or VHDL language, multi-cycle CPU design. Able to complete the following 22 instructions. (Not taking into account the virtual address and the Cache, and the default is big endian): add rd, rs, rt addu rd, rs, rt addi rt, rs, imm addiu rt, rs, imm sub rd, rs, rt subu rd, rs, rt of nor rd, rs, rt xori rt, rs, imm clo clz slt rd, rs, rt sltu rd, rs, rt slti rt, rs, imm sltiu rt, rs, imm sllv rd, rt, rs sra rd, rt, shamt blez rs, imm j target lwl rt, offset (base) lwr rt, offset (base) lw rt, imm (rs) sw rt, imm (rs)
Date : 2025-12-25 Size : 4.84mb User : 徐帆
[VHDL-FPGA-Verilog] mulitcpu DL : 0: 用verilog HDL语言或者VHDL语言来编写，实现多时钟周期CPU的设计。能够完成以下二十二条指定（均不考虑虚拟地址和Cache，并且默认为小端方式）： add rd, rs, rt addu rd, rs, rt addi rt, rs, imm addiu rt, rs, imm sub rd, rs, rt subu rd, rs, rt nor rd, rs, rt xori rt, rs, imm clo clz slt rd, rs, rt sltu rd, rs, rt slti rt, rs, imm sltiu rt, rs, imm sllv rd, rt, rs sra rd, rt, shamt blez rs, imm j target lwl rt, offset(base) lwr rt, offset(base) lw rt, imm(rs) sw rt, imm(rs) -Verilog HDL language or VHDL language to write multi-clock cycle of the CPU design. To complete the following 22 specified (not taking into account the virtual address and the Cache and the default Xiaoduan): add rd, rs, rt addu rd, rs, rt addi rt, rs, imm addiu rt, rs, imm sub rd, rs, rt subu rd, rs, rt of nor rd, rs, rt xori rt, rs, imm clo clz slt rd, rs, rt sltu rd, rs, rt slti rt, rs, imm sltiu rt, rs, imm sllv rd, rt, rs sra rd, rt, shamt blez rs, imm j target lwl rt, offset (base) lwr rt, offset (base) lw rt, imm (rs) sw rt, imm (rs)Undo edits DictionaryGoogle Translate for Business:Translator ToolkitWebsite TranslatorGlobal Market Finder
Date : 2025-12-25 Size : 8.47mb User : 徐帆
[VHDL-FPGA-Verilog] cache DL : 0: 利用VHDL语言，仿真cache与主存的关系，使用了类似数组的方法。-using vhdl,tell us the relation between cache and memory.
Date : 2025-12-25 Size : 329kb User : fq

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