5-stage pipeline without cache, CPU test, is learning VHDL good information, very helpful for understanding the CPU!

config&samples\cpu.txt
..............\ex1.txt
..............\ex2.txt
..............\ex3.txt
..de_VHDL\alu.vhd
.........\ar.vhd
.........\bus_dir.vhd
.........\bus_mux.vhd
.........\controller.vhd
.........\flag_reg.vhd
.........\ir.vhd
.........\pc.vhd
.........\reg.vhd
.........\reg_mux.vhd
.........\reg_out.vhd
.........\reg_test.vhd
.........\reg_testa.vhd
.........\t1.vhd
.........\t2.vhd
.........\t3.vhd
.........\timer.vhd
config&samples
code_VHDL
示例报告_无流水无cache.pdf

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