Verilog MIPS design. I found it somewhere on Internet and it is working :))))

mips1
.....\alu.v
.....\alu_test.v
.....\chipsnooper.v
.....\clkgen.v
.....\cntrlsnooper.v
.....\control.v
.....\datapath.v
.....\datapath_test.v
.....\datasnooper.v
.....\memory.v
.....\pctest.v
.....\regfile.v
.....\regfile_test.v
.....\reglogic.v
.....\reglogic_test.v
.....\stimulus.v
.....\test.v
.....\topsnooper.v

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