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[VHDL-FPGA-Verilog] pipe DL : 0: verilog编写的流水线模块-Verilog modules prepared by the Pipeline
Date : 2025-12-21 Size : 5kb User : 刘陆陆
[VHDL-FPGA-Verilog] add_3p DL : 0: 3级流水线，含4元件的22位全加器的VHDL语言实现，适用于altera系列的FPGA-3-stage pipeline, with 4 components of 22 full adder realize the VHDL language, applicable to altera Series FPGA
Date : 2025-12-21 Size : 2kb User : wgx
[VHDL-FPGA-Verilog] pipeline DL : 0: 关于FPGA设计中的流水线技巧的使用和例子，一个很好的减少硬件消耗的技巧-About FPGA design using pipelining techniques and examples, a good technique to reduce the hardware consumption
Date : 2025-12-21 Size : 1004kb User : JET
[VHDL-FPGA-Verilog] FIFO_8_8 DL : 0: FIFO先进先出队列，一种缓存、或一种管道、设备、接口（Verilog HDL程序,内附说明）-FIFO FIFO queue, a cache, or a pipeline, equipment, Interface (Verilog HDL program, containing a note)
Date : 2025-12-21 Size : 5kb User : 镜子
[VHDL-FPGA-Verilog] float_data_multiple_use_fixed_pipeline_verilog_pro DL : 0: 采用fpga做小数运算的程序，使用了三级流水线技术，这是学习流水线和定点小数乘法很好的例子！-a program of float multiply, using 3-stage pipeline technology
Date : 2025-12-21 Size : 1kb User : xietianjiao
[VHDL-FPGA-Verilog] add DL : 0: 流水线乘法器与加法器开发环境：Modelsim（verilog hdl）-Multiplier and adder pipeline development environment: Modelsim (verilog hdl)
Date : 2025-12-21 Size : 1kb User : 来法旧佛
[VHDL-FPGA-Verilog] waterline_adder DL : 0: 这是一个用Verilog编写的四级流水线加法器-This is a Verilog prepared with four pipeline adder
Date : 2025-12-21 Size : 1kb User : 伊莲幽梦
[VHDL-FPGA-Verilog] cordic DL : 0: vhdl语言编写的cordic算法，实现了cordic的流水线运算。-cordic language vhdl algorithm cordic the pipeline operator.
Date : 2025-12-21 Size : 1kb User : lmy
[VHDL-FPGA-Verilog] fir_512_378_mux DL : 0: 512阶高速FIR成型滤波器，四相位复用，树形加法和多级流水线结构。-512-order high-speed FIR shaping filter, four-phase re-use, tree addition and multi-stage pipeline structure.
Date : 2025-12-21 Size : 29kb User : johnnyz
[VHDL-FPGA-Verilog] 16bit_pipeline DL : 0: 16 bit pipeline design by vhdl.
Date : 2025-12-21 Size : 311kb User : leejp
[VHDL-FPGA-Verilog] arm7 DL : 1: ARM7 VERILOG源码，非常精简，3级流水线-ARM7 VERILOG source code, very streamlined, 3-stage pipeline
Date : 2025-12-21 Size : 169kb User : hcq
[VHDL-FPGA-Verilog] RISC DL : 0: 32 bit RISC Processor with 3 stage pipeline
Date : 2025-12-21 Size : 2.05mb User : rudra
[VHDL-FPGA-Verilog] Cordic123 DL : 0: for the pipeline cordic algorithm .it uses the vhdl language and good code and defines the algoritm correctly-for the pipeline cordic algorithm .it uses the vhdl language and good code and defines the algoritm correctly
Date : 2025-12-21 Size : 107kb User : jai
[VHDL-FPGA-Verilog] post_norm_mul DL : 1: 符合IEEE754标准的32位浮点流水线乘法器采用移位相加算法，-32-bit floating point pipeline multiplier on IEEE754 standard
Date : 2025-12-21 Size : 3kb User : Thomas
[VHDL-FPGA-Verilog] processor DL : 0: processor design istruction load pipeline ,hazard
Date : 2025-12-21 Size : 41kb User : oiwehfoiwaefhp
[VHDL-FPGA-Verilog] PIPE_LINING_CPU_TEAM_24 DL : 0: 采用Quatus II编译环境，使用Verilog HDL语言编写实现了五段流水线CPU。能够完成以下二十二条指令（均不考虑虚拟地址和Cache，并且默认为小端方式）： add rd,rs,rt addu rd,rs,rt addi rt,rs,imm addiu rt,rs,imm sub rd,rs,rt subu rd,rs,rt nor rd,rs,rt xori rt,rs,imm clo rd,rs clz rd,rs slt rd,rs,rt sltu rd,rs,rt slti rt,rs,imm sltiu rt,rs,imm sllv rd,rt,rs sra rd,rt,shamt blez rs,imm j target lwl rt,offset(base) lwl rt,offset(base) lw rt,imm(rs) sw rt,imm(rs) 在本设计中，采取非常良好的模块化编程风格，共分十三个主要模块PIPE_LINING_CPU_TEAM_24.v为顶层实体文件，对应为PIPE_LINING_CPU_TEAM_24模块作为顶层实体模块，如下： ifetch.v、regdec.v、exec.v、mem.v、wr.v分别实现五个流水段； cpuctr.v用于产生CPU控制信号； ALU.v用于对操作数进行相应指令的运算并输出结果； DM.v数据存储器 IM.v指令存储器 datareg.v数据寄存器堆 extender.v位扩展 yiwei_32bits.v 实现32位四种移位方式的移位器在顶层实体中，调用ifetch.v、regdec.v、exec.v、mem.v、wr.v这五个模块就实现了流水线CPU。顶层模块的结构清晰明了。对于学习verilog编程非常有用- Quatus II compiled by the environment, using Verilog HDL language to achieve a five-stage pipeline CPU. To complete the following 22 commands (not considering the virtual address and Cache, and the default mode for the small end): add rd, rs, rt addu rd, rs, rt addi rt, rs, imm addiu rt, rs, imm sub rd, rs, rt subu rd, rs, rt nor rd, rs, rt xori rt, rs, imm clo rd, rs clz rd, rs slt rd, rs, rt sltu rd, rs, rt slti rt, rs, imm sltiu rt, rs, imm sllv rd, rt, rs sra rd, rt, shamt blez rs, imm j target lwl rt, offset (base) lwl rt, offset (base) lw rt, imm (rs) sw rt, imm (rs) In this design, take a very good modular programming style, is divided into 13 main modules PIPE_LINING_CPU_TEAM_24.v for the top-level entity file, the corresponding module as a top-level entity for the PIPE_LINING_CPU_TEAM_24 modules, as follows: ifetch.v, regdec.v, exec.v, mem.v, wr.v water were to achieve the five paragraph cpuctr.v used to generate CPU control signal ALU.v accordingly
Date : 2025-12-21 Size : 4.72mb User : 石
[VHDL-FPGA-Verilog] PipelineCPU DL : 0: 用Verilog实现一个简单的流水线CPU，并运行一个Quicksort程序。这是Berkley，eecs系的计算机系统结构课程实验的实验三。-This file is written in Verilog to achieve a simple pipeline CPU, which can run a Quicksort program.
Date : 2025-12-21 Size : 28kb User : Matgek
[VHDL-FPGA-Verilog] CPU DL : 0: 32位5级流水线CPU设计指令系统、指令格式、寻址方式、寄存器结构、数据表示方式、存储器系统、运算器、控制器和流水线结构等-32bit pipeline CPU
Date : 2025-12-21 Size : 183kb User : znl
[VHDL-FPGA-Verilog] vhdl-pipeline-mips_latest.tar DL : 0: pipeline mips in vhdl
Date : 2025-12-21 Size : 1.08mb User : aliakbar
[VHDL-FPGA-Verilog] PipeLine.tar DL : 0: Verilog实现MIPS五段流水线，22条指令（基本算术、移位和load、store指令），模块化设计，含注释-Verilog realization of five-stage pipeline MIPS 22 instructions (basic arithmetic, shift, and load, store instructions), modular design, with annotations
Date : 2025-12-21 Size : 2.79mb User : czl

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