Search - multiplier

Search - multiplier - List

[VHDL-FPGA-Verilog] 16位快速乘法器 DL : 0: VHDL语言实现的16位快速乘法器-VHDL of 16 rapid Multiplier
Date : 2025-12-17 Size : 3kb User :
[VHDL-FPGA-Verilog] multi_vhdl DL : 0: 四位乘法器的VHDL源程序-four Multiplier VHDL source
Date : 2025-12-17 Size : 1kb User : 张庆辉
[VHDL-FPGA-Verilog] 经典高速乘法器IP DL : 0: 乘法器是硬件设计中的很常见也很重要的一个模块，它的VHDL硬件实现很好的解决了软件编程中做乘法速度慢的问题，在实时高速系统应用中或DSP软核或数字信号处理硬件实现算法中，经常能使用到乘法器，所以经典的高速乘法器IP 很有参考价值-Multiplier is a common and important module in hardware designing.Its VHDL addresses the low speed of multiplication in software programming. Multiplier is often used in real-time high-speed system application , DSP soft core or hardware implementation of digital signal processing,so it is worthful to know classic high-speed multiplier IP
Date : 2025-12-17 Size : 302kb User : czy
[VHDL-FPGA-Verilog] booth_mul DL : 0: 一种可以完成16位有符号／无符号二进制数乘法的乘法器。该乘法器采用了改进的Booth算法，简化了部分积的符号扩展，采用Wallace树和超前进位加法器来进一步提高电路的运算速度。本乘法器可以作为嵌入式CPU内核的乘法单元，整个设计用VHDL语言实现。-a 16 to be completed with symbols/unsigned multiplication of the number of binary multipliers. The multiplier used to improve the Booth algorithm, simplified some of the plot symbols expansion Wallace tree and used-ahead adder circuit to further enhance the computing speed. The multiplier can be used as embedded CPU cores multiplication modules, the entire design with VHDL.
Date : 2025-12-17 Size : 19kb User : 李鹏
[VHDL-FPGA-Verilog] Booth_Multiplier DL : 0: 布斯乘法器的VHDL程序,下載後直接解壓縮複製貼上到你的EDATOOL就可以.-Booth multiplier VHDL procedures downloaded directly extract copy affixed to the EDATOOL you can.
Date : 2025-12-17 Size : 1kb User : 韓堇
[VHDL-FPGA-Verilog] mul6 DL : 0: 用vhdl语言设计CPU中的一部分：乘法器的设计，包括多种乘法器的设计方法！内容为英文-design using VHDL language part of the CPU : multiplier design, Multiplier including multiple design! As for the English
Date : 2025-12-17 Size : 452kb User : qindao
[VHDL-FPGA-Verilog] BoothMultiplier DL : 0: -- Booth Multiplier -- This file contains all the entity-architectures for a complete -- k-bit x k-bit Booth multiplier. -- the design makes use of the new shift operators available in the VHDL-93 std -- this design passes the Synplify synthesis check -- download from: www.fpga.com.cn & www.pld.com.cn--- Booth Multiplier-- This file contains a ll the entity-architectures for a complete-- k- bit x k-bit Booth multiplier.-- the design mak es use of the new shift operators available in th e VHDL-93 std-- this design passes the Synplify synthesis check-- download from : www.fpga.com.cn
Date : 2025-12-17 Size : 2kb User : 罗兰
[VHDL-FPGA-Verilog] lpm_mul DL : 0: ８＊８的乘法器verilog源代码,经过编译仿真的，绝对真确，对初学者很有帮助-8* 8 Multiplier verilog source code, compiled simulation, absolute authenticity, helpful for beginners
Date : 2025-12-17 Size : 27kb User : 刘东辉
[VHDL-FPGA-Verilog] mult8x8 DL : 0: 一个用VerilogHDL语言编写的8X8的乘法器-a Verilog HDL language used in the preparation of the multiplier 8X8
Date : 2025-12-17 Size : 17kb User : 胡东
[VHDL-FPGA-Verilog] multiplier DL : 0: booth乘法器： 16*16有符号乘法器，Booth编码，简单阵列，Ripple Carry Adder-booth multiplier:
Date : 2025-12-17 Size : 3kb User : chenyi
[VHDL-FPGA-Verilog] Multiplier DL : 0: 乘法器所占资源很少很好的一个乘法器史书上的一个例子说得很好啊-Multiplier good share of scarce resources in the history books on a multiplier an example of very good
Date : 2025-12-17 Size : 349kb User : jack yao
[VHDL-FPGA-Verilog] 8-bit-Multiplier DL : 0: 一种基于加法器树方法的8为乘法器的VHDL源码，该方法虽然相对占有资源多，但仿真快-VHDLSourceProgramof8-bit-Multiplier
Date : 2025-12-17 Size : 1kb User : 杨波
[VHDL-FPGA-Verilog] Multiplier DL : 0: BJ-EPM240V2实验例程以及说明文档实验之五乘法器设计-BJ-EPM240V2 experimental test routines as well as documentation of the five multiplier design
Date : 2025-12-17 Size : 472kb User : 王建毅
[VHDL-FPGA-Verilog] multiplier DL : 0: 该乘法器是由8位加法器构成的以时序方式设计的8位乘法器。其乘法原理是：乘法通过逐项移位相加原理来实现，从被乘数的最低位开始，若为1，则乘数左移后与上一次的和相加；若为0，左移后以全零相加，直至被乘数的最高位。-The multiplier is 8-bit adder consisting of time-series design to the 8-bit multiplier. The multiplication principle is: the sum of multiplication through the principle of each shift to achieve, from the beginning of the lowest multiplicand, if 1, then left after the multiplier and the sum of the last if for 0, left after zero-sum in full, until the highest bit multiplicand.
Date : 2025-12-17 Size : 101kb User : lsp
[VHDL-FPGA-Verilog] Multiplier DL : 0: It s a design of a 4*4 multiplier based on Verilog, using Xilinx ISE.
Date : 2025-12-17 Size : 839kb User : wayne
[VHDL-FPGA-Verilog] multiplier-accumulator(vhdl) DL : 0: 用VHDL语言描述和实现乘法累加器设计,4位的被乘数X和4位的乘数Y输入后，暂存在寄存器4位的寄存器A和B中，寄存器A和B的输出首先相乘，得到8位乘积，该乘积再与8位寄存器C的输出相加，相加结果保存在寄存器C中。寄存器C的输出也是系统输出Z。(原创，里面有乘法部分和累加部分可以单独提出来，很好用) -With the VHDL language to describe the design and realization of multiplier-accumulator, four of multiplicand X and 4-bit multiplier Y input, the temporary 4-bit registers in the register A and B, registers A and B multiplied by the output of the first, to be 8-bit product, the product further with the 8-bit output of register C, the sum of, the sum of the results stored in register C,. The output register C is also the system output Z. (Original, which are multiply and accumulate some part may be raised separately, very good use)
Date : 2025-12-17 Size : 945kb User : jlz
[VHDL-FPGA-Verilog] floating-point-multiplier DL : 0: verilog implementation of the floating point multiplier
Date : 2025-12-17 Size : 1kb User : ramtin
[VHDL-FPGA-Verilog] Multiplier DL : 0: 时序乘法器，verilog编写，速度慢，但消耗资源少，时钟沿到来时，输入/输出1bit数据-Sequential multiplier, verilog written, slow, but consume fewer resources, the clock edge arrives, the input/output 1bit data
Date : 2025-12-17 Size : 205kb User : 大兵
[VHDL-FPGA-Verilog] PARALLEL-MULTIPLIER DL : 0: vhdl code for a 32 bit parallel multiplier
Date : 2025-12-17 Size : 7kb User : sandeep kumar
[VHDL-FPGA-Verilog] binary multiplier DL : 0: verilog code for binary multiplier
Date : 2025-12-17 Size : 3.58mb User : krisna

« 12 3 4 5 6 7 8 9 10 ... 35 »