Search - The C Programming Language

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[VHDL-FPGA-Verilog] DDS_Power DL : 0: FPGA上的VERILOG语言编程。通过查找表实现直接数字频率合成。在主控部分通过键盘选择正弦波，方波，三角波，斜波，以及四种波形的任意两种的叠加，以及四种波形的叠加；通过控制频率控制字C的大小，以控制输出波形频率，实现1Hz的微调；通过地址变换实现波形相位256级可调；通过DAC0832使波形幅值256级可调；通过FPGA内部RAM实现波形存储回放；并实现了每秒100HZ扫频。-FPGA on the verilog language programming. Lookup table through direct digital frequency synthesis. In part through the control of the keyboard to choose sine, square, triangle wave, sloping wave, and four arbitrary waveform two superposed and the stack of four waveform; by controlling the frequency control word on the size, in order to control the output waveform frequency, 1 Hz to achieve the fine-tuning; Address transform through waveform phase adjustable 256; DAC0832 so through waveform amplitude adjustable 256; FPGA through internal RAM to the waveform storage intervals; and achieve a 100 per second sweep 9999.
Date : 2025-12-19 Size : 16kb User : 田世坤
[VHDL-FPGA-Verilog] 2 DL : 0: 针对C语言编程者的Verilog开发指南实例-C language programming for the development of guidelines for examples of Verilog
Date : 2025-12-19 Size : 133kb User : pan
[VHDL-FPGA-Verilog] Eat_beans_on_the_8086_games DL : 0: 本项目在FPGA上生成8086指令兼容的软核以及外设，并在此基础上跑通pc机上古老但是仍然有趣的吃豆子PACMAN游戏，作为本科微机原理课程的实验。通过本项目，学生可以学习到8086的基本结构，在TurboC下如何进行嵌入式C语言编程，汇编语言，计算机组成等基本原理，有独立设计基于8086的SOC软硬件的能力。-The project generated in the FPGA on the 8086 Directive, as well as soft-core-compatible peripherals, and on this basis pc machine running the old pass is still fun to eat but beans PACMAN game, as a principle of undergraduate courses in computer experiments. Through the project, students learn the basic structure of 8086, in TurboC how embedded C language programming, assembly language, computer components, such as the basic principles, independent of the SOC design is based on the 8086 hardware and software capabilities.
Date : 2025-12-19 Size : 5.99mb User : xiaoxu
[VHDL-FPGA-Verilog] vhdl DL : 0: 循环码编译码程序，用c语言编程的该for 循环计算码组的后3 个码元-Cyclic code encoding and decoding procedures, with c language programming cycle of the calculation of the code group for the three yards after the yuan
Date : 2025-12-19 Size : 13kb User : 小小
[VHDL-FPGA-Verilog] NovakodStudio DL : 0: For all thoses interested in a new language and programming paradigm. This is a complete IDE for programming in the psC - Parallel and synchronous C- Language. This language is a high level replacement for VHDL/verilog.-For all thoses interested in a new language and programming paradigm. This is a complete IDE for programming in the psC - Parallel and synchronous C- Language. This language is a high level replacement for VHDL/verilog.
Date : 2025-12-19 Size : 14.59mb User : Luc
[VHDL-FPGA-Verilog] workspace0823 DL : 0: 这是我写的基于xilinx公司的virtex5版本fpga的network底层程序，其中是C语言与API混合编程，希望对用得着的兄弟有些帮助。-This is what I wrote based company virtex5 xilinx fpga of the network version of the underlying process, which is a mixture of C programming language and API, the brothers want to need it some help.
Date : 2025-12-19 Size : 6.66mb User : 曾亮
[VHDL-FPGA-Verilog] FPGA-Kai-Fa-Ban.REV2.0 DL : 0: 本产品教程与注亍NIOS Ⅱ嵌入式开収,主要由C诧言开収,因此,打好C诧言的基础很重要,在此推荐一本《C程序设计诧言》(第2版),英文名为《The C Programming Language》(Second Edition),该书是由C诧言的设计者Brian W.Kernighan和Dennis M.Ritchie编写的一部介绍标准C诧言及其程序设计方法的权威性经典著作。全面、系统地讱述了C诧言的各个特性及程序设计的基本方法，包括基本概念，类型和表达式、控制流、函数不程序结构、指针不数组、结构、输入不输出、UNIX系统接口、标准库等内容-Note this product tutorials and close right foot to open the embedded NIOS Ⅱ, made mainly by the C surprised to open closed, therefore, to lay the basis for C is very important words surprised at this recommendation a " C Programming surprised Introduction" (2nd edition) , the English called " The C Programming Language" (Second Edition), surprised the book made by the designers of C Brian W. Kernighan and Dennis M. Ritchie introduced a prepared statement surprised the standard C programming method and its authority classics. Comprehensive, systematic Ren surprised statement describes the various characteristics of C and the basic method of programming, including basic concepts, types and expressions, control flow, function does not program structure, pointers are not arrays, structures, input not output, UNIX System Interface , the standard library, etc.
Date : 2025-12-19 Size : 1.86mb User : liyucai
[VHDL-FPGA-Verilog] CoreI2C DL : 0: Actel公司FPGA fusion系列M1AFS600的I2C实验的FPGA程序和keil环境下C语言程序，程序测试通过。-Actel Corporation FPGA fusion experimental series M1AFS600 the I2C FPGA procedures and keil C language programming environment, the program test.
Date : 2025-12-19 Size : 14.6mb User : 卫菊梅
[VHDL-FPGA-Verilog] LCD DL : 0: Actel fusion M1AFS600的LCD实验，基于周立功公司CortexM1开发板，程序包括FPGA源程序和Keil环境下C语言程序，程序测试通过。-Actel fusion M1AFS600 the LCD test, Zhou, who based the company CortexM1 development board, the program includes FPGA source code and Keil C language programming environment, the program test.
Date : 2025-12-19 Size : 10.95mb User : 卫菊梅
[VHDL-FPGA-Verilog] Fir51 DL : 0: impulse 实现的fir 51阶C语言编程，可转换为HDL语言-The impulse to realize fir 51 order the C programming language, can convert to HDL language
Date : 2025-12-19 Size : 87kb User : 石头
[VHDL-FPGA-Verilog] PIC24 DL : 0: 此文档包含PIC16位单片机的C语言编程例程，包括液晶显示屏，按键检测，UART通信，SPI通信，A/D转换等，对16位单片机学习者有很大的帮户作用。-This document contains the PIC16 bit microcontroller C programming language routines, including LCD display, key detection, the UART communication, SPI communication, A/D conversion, 16-bit microcontroller learners a great help user role.
Date : 2025-12-19 Size : 858kb User : 许万鹏
[VHDL-FPGA-Verilog] verilogHDL DL : 0: 针对C 语言编程者的Verilog 开发指南实例包括完全用软件实现的位脉冲PWM 控制器等-Fully implemented in software-bit pulse PWM controller instance for the C programming language Verilog Developer s Guide
Date : 2025-12-19 Size : 151kb User : 朴圣龙
[VHDL-FPGA-Verilog] PERI4-DM9000A DL : 0: 基于FPGA的DM9000A芯片的网络数据采集系统，基于NIOS架构，c语言编程，资料齐全，包含不止5个源程序，绝对受用！-FPGA-based the DM9000A chip network data acquisition system based on NIOS architecture, c programming language, the information is complete, contains more than 5 source code is absolutely good enough!
Date : 2025-12-19 Size : 16.48mb User : mingbo
[VHDL-FPGA-Verilog] TrafficLight DL : 0: 通过硬件描述语言VHDL编程，实现交通灯功能，要求如下：　　① 车辆传感器（C），检测车辆通行情况，用于主干道的优先权控制； ② 主干道公路路口安装有人员通过请求按钮（PQ），一旦有请求信息，控制器应按放行处理，否则按默认方式处理； ③ Online控制信号由交通控制中心发出，（Online=1）一旦它有效，则主干道放行，十字交叉路口控制器“失效”，Online=0十字交叉路口控制器恢复控制权；　　④ 当次干道公路无车时，始终保持次干道公路红灯亮，主干道绿灯亮； ⑤ 当次干道公路有车时，而主干道通车时间已经超过它的最短通车时间时，禁止主干道通行，让次干道公路通行。主干道最短通车时间为25s ； ⑥ 当次干道公路和主干道都有车时，按主干道通车25s，次干道公路通车16s交替进行；　　⑦ 不论主干道情况如何，次干道公路通车最长时间为16s； ⑧ 在每次由绿灯亮变成红灯亮的转换过程中，要亮5s时间的黄灯作为过渡； ⑨ 用两组开关代替传感器作为检测人员通过请求和车辆是否到来的信号。用红、绿、黄三种颜色的发光二极管作交通灯；　　⑩ 要求显示时间，倒计时。-Through hardware description language VHDL programming, traffic lights functional requirements are as follows: ① vehicle sensors (C), detection of vehicle traffic situation, the priority control for the main road ② trunk road junctions equipped with staff through a request button (PQ), if there is a request message, the controller should be released, otherwise handled by default ③ Online control signal issued by the traffic control center, (Online = 1) if it is valid, trunk release, cross the intersection Controller "failure", Online = 0 crossroad controller resumes control over ④ When the secondary trunk road no car, and always maintain secondary roads road red light, green light main road ⑤ When the secondary trunk road with the car, while the trunk opening time has exceeded its minimum opening time, prohibited roads impassable, so that secondary roads roads impassable. Trunk shortest time for the opening 25s ⑥ When the sub-trunk roads and main roads have vehicle, accordin
Date : 2025-12-19 Size : 8.51mb User : 韩彩英
[VHDL-FPGA-Verilog] UART DL : 0: 本代码用verilog语言配合sopc和nios实现了串口调试的目的。软件编程用C语言描述，只是比较简单的例子，适合初学者做了解用，本人亲自在EP2C8Q上实践。-The code to use verilog language sopc and nios achieved with serial debugging purposes. Software programming using C language description, but relatively simple example for beginners to do with understanding, I personally EP2C8Q on practice.
Date : 2025-12-19 Size : 17.04mb User : 普尔