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  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
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Actel Corporation FPGA fusion experimental series M1AFS600 the I2C FPGA procedures and keil C language programming environment, the program test.
Packet file list
(Preview for download)
CoreI2C\ACTL_Prj\CortexM1\constraint\CortexM1_top.dtf\core.ddf
.......\........\........\..........\CortexM1_top.pdc
.......\........\........\..reconsole\common\CoreAHB2APB\CoreAHB2APB.cxf
.......\........\........\...........\......\...........\rtl\verilog\o\CoreAHB2APB.v
.......\........\........\...........\......\.......Lite\CoreAHBLite.cxf
.......\........\........\...........\......\...........\coreparameters.v
.......\........\........\...........\......\...........\rtl\verilog\o\CoreAHBLite.v
.......\........\........\...........\......\...........\...\.......\.\Decoder.v
.......\........\........\...........\......\...........\...\.......\.\DefaultSlave.v
.......\........\........\...........\......\...........\...\.......\.\MuxS2M.v
.......\........\........\...........\......\.....PB\CoreAPB.cxf
.......\........\........\...........\......\.......\coreparameters.v
.......\........\........\...........\......\.......\rtl\verilog\o\CoreAPB.v
.......\........\........\...........\......\.......\...\.......\.\MuxP2B.v
.......\........\........\...........\......\....GPIO\bfm\CoreGPIO_scriptlet.bfm
.......\........\........\...........\......\........\CoreGPIO.cxf
.......\........\........\...........\......\........\coreparameters.v
.......\........\........\...........\......\........\rtl\verilog\o\CoreGPIO.v
.......\........\........\...........\......\.OREI2C\COREI2C.cxf
.......\........\........\...........\......\.......\coreparameters.v
.......\........\........\...........\......\.......\mti\lib_vlog_obs\COREI2C_LIB\_info
.......\........\........\...........\......\.......\...\scripts\wavetb_vlog.do
.......\........\........\...........\......\.......\rtl\vlog\core_obfuscated\corei2c.v
.......\........\........\...........\......\.......\...\....\...............\corei2creal.v
.......\........\........\...........\......\.......\...\....\test\user\smbus_wrp.v
.......\........\........\...........\......\.......\...\....\....\....\testbench.v
.......\........\........\...........\......\.oreInterrupt\bfm\CoreInterrupt_scriptlet.bfm
.......\........\........\...........\......\.............\CoreInterrupt.cxf
.......\........\........\...........\......\.............\coreparameters.v
.......\........\........\...........\......\.............\rtl\verilog\o\CoreInterrupt.v
.......\........\........\...........\......\....MemCtrl\bfm\CoreMemCtrl_scriptlet.bfm
.......\........\........\...........\......\...........\CoreMemCtrl.cxf
.......\........\........\...........\......\...........\coreparameters.v
.......\........\........\...........\......\...........\rtl\verilog\o\CoreMemCtrl.v
.......\........\........\...........\......\....Remap\bfm\CoreRemap_scriptlet.bfm
.......\........\........\...........\......\.........\CoreRemap.cxf
.......\........\........\...........\......\.........\rtl\verilog\o\CoreRemap.v
.......\........\........\...........\......\....UARTapb\coreparameters.v
.......\........\........\...........\......\...........\CoreUARTapb.cxf
.......\........\........\...........\......\...........\mti\lib_vlog_obs\COREUARTAPB_LIB\@c@o@r@e@u@a@r@t\verilog.psm
.......\........\........\...........\......\...........\...\............\...............\................\_primary.dat
.......\........\........\...........\......\...........\...\............\...............\................\_primary.vhd
.......\........\........\...........\......\...........\...\............\...............\................apb\verilog.psm
.......\........\........\...........\......\...........\...\............\...............\...................\_primary.dat
.......\........\........\...........\......\...........\...\............\...............\...................\_primary.vhd
.......\........\........\...........\......\...........\...\............\...............\...u@a@r@t@o1\verilog.psm
.......\........\........\...........\......\...........\...\............\...............\.............\_primary.dat
.......\........\........\...........\......\...........\...\............\...............\.............\_primary.
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