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[VHDL-FPGA-Verilog] verilog-Perl-3.120.tar DL : 0: Verilog Parser in Perl
Date : 2026-01-10 Size : 160kb User : prakash
[VHDL-FPGA-Verilog] fracn09 DL : 0: Clock generation perl to vhdl oijoij
Date : 2026-01-10 Size : 27kb User : Alduraibi
[VHDL-FPGA-Verilog] all_packages_20080525.tar DL : 0: FMF VHDL Models All the FMF models are VHDL 93 and VITAL 2000 compliant and require the VITAL 2000 library for correct compilation. They are designed for timing backannotation by means of an SDF file. The intrinsic delays default to 1 ns. We have a tool to read internal delays from an external file (in XML) and add them to the simulation through a SDF file. The most recent version is written in perl and may be downloaded from the "FMF Tools" area. Timing files are provided for over 11,500 part numbers. Also in the tools area is the document type definition (dtd) for the timing files. FMF MAKES NO WARRANTIES ON THE PERFORMANCE OF ANY MODELS IN ITS DATA REPOSITORY. USERS ARE RESPONSIBLE FOR VERIFYING THE ACCURACY OF THE MODELS, SOFTWARE OR TOOLS PROVIDED (TEST SUITES, PACKAGES, TIMING, ETC.).
Date : 2026-01-10 Size : 20kb User : ledo
[VHDL-FPGA-Verilog] perl DL : 0: perl学习资料，包含一些常用的一些文档，可直接做来用于实践-perl training
Date : 2026-01-10 Size : 1.44mb User : yoarst
[VHDL-FPGA-Verilog] PERL_PROGRAM DL : 0: perl program for generating test vector and veryfying test vector useful for VHDL design verification
Date : 2026-01-10 Size : 2kb User : arun
[VHDL-FPGA-Verilog] HowtousePerlinyourVerilogHDLDesignFlow DL : 0: use Perl in your Verilog HDL Design Flow,利用Perl语言方便管理Verilog HDL 代码。-How to use Perl in your Verilog HDL Design Flow
Date : 2026-01-10 Size : 16kb User : 张
[VHDL-FPGA-Verilog] VerilogPreprocessing DL : 0: 使用 Perl语言 ,采用面向对象的编程 (OOP) 方法 ,讨论了一种 Verilog预处理工具的设计.-Using the Perl language, object-oriented programming (OOP) method, discussed the design of a Verilog preprocessing tool.
Date : 2026-01-10 Size : 398kb User : guoj
[VHDL-FPGA-Verilog] fpga DL : 0: Date : 2026-01-10 Size : 17kb User : aa
[VHDL-FPGA-Verilog] verilog_testbench_genetator DL : 0: 这是一个perl程序只需要在cmd中运行，参数为你的Verilog名字功能是:半自动生成Verilog的testbench，提高编码效率-#-----READ ME of verilog_tb_generate.pl----------------------| # | #-----copyright(C) Xzmeng 2010-------------------------------| # | #Date:2010-12-18 21:55:48------------------------------------| # | #Run the pl followed with the verlog file name,such as aaa.v | #Put the original verilog file(.v) in the current directory. | #------------------------------------------------------------| # | #And you need to gurrantee that there is only one "input" or | #"output" per line. | # | #------------------------------------------------------------|
Date : 2026-01-10 Size : 2kb User : zishan
[VHDL-FPGA-Verilog] Perl_for_CRC DL : 0: Cyclic Redundancy Check (CRC) is an error-checking code that is widely used in data communication systems and other serial data transmission systems. CRC is based on polynomial manipulations using modulo arithmetic. Some of the common Cyclic Redundancy Check standards are CRC-8, CRC-12, CRC-16, CRC-32, and CRC-CCIT. This application note discusses the implementation of an IEEE 802.3 CRC in a Virtex™ device. The reference design provided with this application note provides Verilog point solutions for CRC-8, CRC-12, CRC-16, and CRC-32. The Perl script (crcgen.pl) used to generate this code is also included. The script generates Verilog source for CRC circuitry of any width (8, 12, 16, 32), any polynomial, and any data input width.-Cyclic Redundancy Check (CRC) is an error-checking code that is widely used in data communication systems and other serial data transmission systems. CRC is based on polynomial manipulations using modulo arithmetic. Some of the common Cyclic Redundancy Check standards are CRC-8, CRC-12, CRC-16, CRC-32, and CRC-CCIT. This application note discusses the implementation of an IEEE 802.3 CRC in a Virtex ™ device. The reference design provided with this application note provides Verilog point solutions for CRC-8 , CRC-12, CRC-16, and CRC-32. The Perl script (crcgen.pl) used to generate this code is also included. The script generates Verilog source for CRC circuitry of any width (8, 12, 16, 32 ), any polynomial, and any data input width.
Date : 2026-01-10 Size : 88kb User : 尤恺元
[VHDL-FPGA-Verilog] testbench-from-perl DL : 0: 直接生成testbench的perl脚本-The software can produce test bench directly by perl
Date : 2026-01-10 Size : 3kb User : 贺铮
[VHDL-FPGA-Verilog] perl DL : 0: perl脚本的一些初步入门知识，对于以后熟练掌握帮助很大-perl script started some preliminary knowledge of great help for the future master
Date : 2026-01-10 Size : 1.44mb User : 张一凡
[VHDL-FPGA-Verilog] blif2vhdl-v1.1 DL : 0: 将BLIF（Berkeley Logic Interchange Format）格式的电路转换为VHDL代码，使用perl编写，需要perl环境才能使用。内含BLIF格式的官方说明。-Translate BLIF（Berkeley Logic Interchange Format）circuit to VHDL description, the translator need perl environment to run. Please check you have related tools. Also include a offical document about BLIF explanation.
Date : 2026-01-10 Size : 70kb User : wangzil
[VHDL-FPGA-Verilog] wb_uart_latest.tar DL : 0: 实现一个一16750/16550 UART。该UART内核是完全基于另一个OpenCores的项目：UART_16750塞巴斯蒂安维特。请找到有关于UART内核的文档。该接口是现在有8位Wishbone总线兼容。随着GHDL模拟器只需运行： ./ghdl_uart.bat 使用任何其他模拟器，开始模拟以下perl脚本必须运行之前： uart_test_stim.pl> FILENAME.TXT 其中，FILENAME.TXT是通用的“stim_file”选择内部wb8_uart_transactor.vhd的名称。正确的模拟应退出并断言消息“模拟END”。-Implements a 16550/16750 UART. The UART core is fully based on another OpenCores project: UART_16750 by Sebastian Witt. Please find there the documentation regarding the Uart core. The interface is now compatible with a 8-bit WishBone bus. With GHDL simulator simply run: ./ghdl_uart.bat Using any other simulator, before starting the simulation the following perl script must be run: uart_test_stim.pl > filename.txt where filename.txt is the name selected in generic stim_file inside wb8_uart_transactor.vhd. A correct simulation should exit with an assertion message simulation END .
Date : 2026-01-10 Size : 21kb User : 包
[VHDL-FPGA-Verilog] crc_verilog_xilinx DL : 0: 包括下面文档： readme.txt : This file crc8_8.v : CRC-8, 8-bit data input. crc12_4.v : CRC-12, 4-bit data input. crc16_8.v : CRC-16, 8-bit data input. crc_ccit_8.v : CRC-CCIT, 8-bit data input. crc32_8.v : CRC-32, 8-bit data input. crcgen.pl : Perl script used to generate Verilog Source for CRC caluculation.(Contains the following files readme.txt : This file crc8_8.v : CRC-8, 8-bit data input. crc12_4.v : CRC-12, 4-bit data input. crc16_8.v : CRC-16, 8-bit data input. crc_ccit_8.v : CRC-CCIT, 8-bit data input. crc32_8.v : CRC-32, 8-bit data input. crcgen.pl : Perl script used to generate Verilog Source for CRC caluculation.)
Date : 2026-01-10 Size : 10kb User : chris_lj