Search - multiplier

Search - multiplier - List

[DSP program] MulPar DL : 0: 八位乘法器VHDL语言实现。使用的工具的ISE7.1，实现八乘八的位相乘。-8 Multiplier VHDL language. Tools used ISE7.1, realize eight by eight-bit multiplication.
Date : 2025-12-17 Size : 2kb User : 周东永
[DSP program] mul88 DL : 0: vhdl语言编写的8X8的乘法器，可运行-vhdl language of the 8X8 of the multiplier, can be run
Date : 2025-12-17 Size : 251kb User : cheng
[DSP program] FFT_based_on_DSP DL : 0: 快速傅氏变换（FFT）是离散傅氏变换的快速算法，它是根据离散傅氏变换的奇、偶、虚、实等特性，对离散傅立叶变换的算法进行改进获得的。它对傅氏变换的理论并没有新的发现，但是对于在计算机系统或者说数字系统中应用离散傅立叶变换，可以说是进了一大步。数字信号处理器(DSP)是一种可编程的高性能处理器，近年来发展很快．它不仅适用于数字信号处理，而且在图像处理、语音处理、通信等领域得到了广泛的应用．通用的微处理器在运算速度上很难适应信号实时处理的要求．联沪处理器中集成有高速的乘法器硬件，能快速地进行大量数据的乘法和加法运算。快速傅里叶变换(FFT)的出现使得DFr在实际应用中得到了广泛的应用．-Fast Fourier Transform (FFT) is the Discrete Fourier Transform Algorithm, which is the discrete Fourier transform of the odd and even, true, real and other properties, on the discrete Fourier transform algorithm was modified to obtain. Fourier transform theory it is not a new discovery, but for the computer systems or digital systems using discrete Fourier transform, can be said that a big step into. Digital signal processor (DSP) is a programmable high-performance processor, developed rapidly in recent years. It is not only applicable to digital signal processing, and image processing, speech processing, communications and other fields has been widely used. General computing speed of microprocessors is difficult to adapt in real-time signal processing requirements. Contact Shanghai high-speed processor integrated hardware multiplier, can carry large amounts of data fast multiplication and addition operations. Fast Fourier Transform (FFT) of the DFR s emergence made in practical applic
Date : 2025-12-17 Size : 343kb User : Raymond
[DSP program] DSP-shiyanzhidao DL : 0: 可编程DSP芯片是一种具有特殊结构的微处理器，为了达到快速进行数字信号处理的目的，DSP芯片一般都具有程序和数据分开的总线结构、流水线操作功能、单周期完成乘法的硬件乘法器以及一套适合数字信号处理的指令集。-Programmable DSP chip is a special structure of the microprocessor in order to achieve rapid digital signal processing, DSP chips generally have a separate program and data bus architecture, pipelining feature, a single cycle to complete the multiplication hardware multiplier as well as a suitable digital signal processing instruction set.
Date : 2025-12-17 Size : 49kb User : 不睡
[DSP program] mul DL : 1: CCS环境下，在DSP硬件板上实现矩阵乘法器。-CCS environment matrix multiplier in DSP hardware board.
Date : 2025-12-17 Size : 75kb User : wu
[DSP program] PLL_test DL : 0: 基于DSP6713，对DSP内的锁相环相关的寄存器进行设置，实现锁相环倍频功能，DSP入门级资料。-Based on the DSP6713, the DSP phase-locked loops in the relevant register set, realization of PLL frequency multiplier function, DSP entry-level data.
Date : 2025-12-17 Size : 1.13mb User : 李华
[DSP program] Ex3_4 DL : 1: 两个16位整数相乘，乘积总是“向左增长”，这意味着多次相乘后乘积将会很快超出定点器件的数据范围。而且要将32位乘积保存到数据存储器，就要开销2个机器周期以及2个字的程序和RAM单元；并且，由于乘法器都是16位相乘，因此很难在后续的递推运算中，将32位乘积作为乘法器的输入。然而，小数相乘，乘积总是“向右增长”，这就使得超出定点器件数据范围的是我们不太感兴趣的部分。在小数乘法下，既可以存储32位乘积，也可以存储高16位乘积，这就允许用较少的资源保存结果，也便于用于递推运算中。这就是为什么定点DSP芯片都采用小数乘法的原因。-Two 16-bit integers, the product is always " left growth" , which means the multiplication product of several fixed devices will soon exceed the range of data. And you want to save the 32-bit product into the data memory, it is necessary overhead two machine cycles, and two words of program and RAM unit And, because the multiplier is multiplied by 16, it is difficult in subsequent recursive arithmetic , the product of a multiplier 32-bit input. However, the fractional multiplication, multiplication always " right growth" , which makes the range of data beyond the fixed-point devices are not interested in our part. Under the fractional multiplication, both 32-bit product may be stored, the upper 16 bits can be stored product, which allows to save the results with fewer resources, but also easy for recursive computations. This is why the fixed-point DSP chips are used decimal multiplication causes.
Date : 2025-12-17 Size : 4kb User : laozhao
[DSP program] book3e DL : 0: 数字信号处理的FPGA实现随书光盘，包含大量Verilog代码，包括加法器，乘法器以及FIR滤波器设计，快速傅立叶变换-FPGA digital signal processing to achieve the CD with the book, contains a large amount of Verilog code, including the adder, multiplier and FIR filter design, fast Fu Liye transform
Date : 2025-12-17 Size : 1.78mb User : 刘许军
[DSP program] booth DL : 0: booth算法的乘法器设置及实现，使用VHDL语言编写-booth algorithm multiplier setting and implementation using VHDL language
Date : 2025-12-17 Size : 1kb User : wanwan