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[Embeded-SCM Develop] lpc2132mydemo DL : 0: lpc2132演示程序,同样是\"基于硬件FIFO和缓冲队列的\"串口收发演示，-lpc2132 demo program, it is also a "hardware-based buffer FIFO Queue and the" serial transceivers demonstration
Date : 2008-10-13 Size : 74.43kb User : h
[Embeded-SCM Develop] FIFO DL : 0: 介绍异步FIFO结构的，对搞微电子的有用
Date : 2008-10-13 Size : 532.92kb User : 华
[Embeded-SCM Develop] 异步fifo的两种经典设计 DL : 0: 异步fifo的两种经典设计，英文文章，里面含有verilog源代码
Date : 2009-10-30 Size : 215.41kb User : handsomexun
[Embeded-SCM Develop] verilog.HDL.examples DL : 0: 许多非常有用的 Verilog 实例: ADC, FIFO, ADDER, MULTIPLIER 等-many very useful Verilog examples : ADC, FIFO, ADDER, MULTIPLIER etc.
Date : 2025-12-21 Size : 184kb User : 张驰
[Embeded-SCM Develop] FIFO DL : 0: 介绍异步FIFO结构的，对搞微电子的有用-Asynchronous FIFO structure introduced on the usefulness of engaging in micro-electronics
Date : 2025-12-21 Size : 533kb User : 华
[Embeded-SCM Develop] fifov1 DL : 0: FIFO（先进先出队列）通常用于数据的缓存和用于容纳异步信号的频率或相位的差异。本FIFO的实现是利用双口RAM 和读写地址产生模块来实现的.FIFO的接口信号包括异步的写时钟（wr_clk）和读时钟（rd_clk）、与写时钟同步的写有效（wren）和写数据（wr_data）、与读时钟同步的读有效（rden）和读数据（rd_data）为了实现正确的读写和避免FIFO的上溢或下溢，给出与读时钟和写时钟分别同步的FIFO的空标志（empty）和满标志（full）以禁止读写操作。-FIFO (FIFO queue) is usually used for data caching and asynchronous signal used to accommodate the frequency or phase differences. The realization of this FIFO is to use dual-port RAM and to read and write address generator module achieved. FIFO interface signals, including asynchronous write clock (wr_clk) and read clock (rd_clk), and write effectively write clock synchronization (wren) and write data (wr_data), clock synchronization and time effective reading (rden) and read data (rd_data) in order to realize the right to read and write and to avoid FIFO overflow or the underflow, is given with the time clock and write clock synchronization FIFO respectively empty signs (empty) and full logo (full) to prohibit the read and write operations.
Date : 2025-12-21 Size : 370kb User : lsg
[Embeded-SCM Develop] ARM_UART DL : 0: 基于arm—LPC2103的串口通讯程序，用上了uart 的FIFO实现。-Arm-LPC2103-based serial communication program, with the use of the UART
Date : 2025-12-21 Size : 51kb User : chengjiang
[Embeded-SCM Develop] FIFO64 DL : 0: FIFO级联，利用verilog语言实现Xilinx FIFO18单元的多个级联，增大FIFO深度。-FIFO cascade, using Verilog Xilinx FIFO18 language to achieve a number of cascade units, increasing the FIFO depth.
Date : 2025-12-21 Size : 3kb User : blackmew
[Embeded-SCM Develop] fifo_core DL : 0: 经典的FIFO实现源码，里面有三种类型，是xilinx工程师写的，经典-Classic source FIFO implementation, there are three types, are written by xilinx Engineer, classical
Date : 2025-12-21 Size : 10kb User : 刘太联
[Embeded-SCM Develop] uart_fifo DL : 0: avr单片机串口先进先出实例程序，这是个人在实际项目中应用的一个例子，还有是定时器的使用方法-Examples of single-chip FIFO serial avr procedures, which are individual projects in the actual application of an example are also the use of timer
Date : 2025-12-21 Size : 16kb User : 张子凤
[Embeded-SCM Develop] FIFO_test DL : 0: FIFO程序库,添加即可使用,一个非常实用的程序-FIFO library, add to the use of
Date : 2025-12-21 Size : 22kb User : 街角的蜗牛
[Embeded-SCM Develop] fifo.tar DL : 0: linux device driver for fifo algorithm
Date : 2025-12-21 Size : 3kb User : sasi
[Embeded-SCM Develop] afifo_0916 DL : 0: 异步FIFO，使用XILINX产品实现，可以通过改参数来重新修改深度和位宽-Asynchronous FIFO, using the XILINX product realization, you can change parameters to re-modify the depth and Width
Date : 2025-12-21 Size : 151kb User : 范小虎
[Embeded-SCM Develop] multiproc-fifo DL : 0: Arm嵌入式系统,进程间通信的一个C语言程序！-ARM programming, multiple process communication!
Date : 2025-12-21 Size : 26kb User : paul
[Embeded-SCM Develop] usb DL : 0: EZUSB开发总结-固件部分，包含EZUSB开发中固件设计，个人小结，适合初学者快速入门，包含FX2 Slave FIFO，Slave FIFO Firmware及一些资料 -EZUSB Development Summary- firmware part, including EZUSB development of firmware design, personal summary, quick start for beginners, including FX2 Slave FIFO, Slave FIFO Firmware and some information
Date : 2025-12-21 Size : 341kb User : 嘻哈天王
[Embeded-SCM Develop] FIFO DL : 0: FIFO设计的难点在于怎样判断FIFO的空/满状态。为了保证数据正确的写入或读出，而不发生益处或读空的状态出现，必须保证FIFO在满的情况下，不能进行写操作。在空的状态下不能进行读操作。怎样判断FIFO的满/空就成了FIFO设计的核心问题。-FIFO design challenge is how to decide the FIFO empty/full. In order to ensure the correct data is written or read, or read the benefits without the risk of the state space, there must be to ensure FIFO in the full circumstances, not for writing. In the empty state can not be read. How to determine the FIFO full/empty FIFO design has become the core issue.
Date : 2025-12-21 Size : 11kb User : 王杰
[Embeded-SCM Develop] FX2-Slave-FIFO DL : 0: usb芯片CY7C68013A例程,接口类型被动先进先出-passive first-in, first-out the usb chip CY7C68013A routine, interface type FIFO
Date : 2025-12-21 Size : 66kb User : 于锋
[Embeded-SCM Develop] fifo DL : 0: FIFO的VHDL代码，最简单的同步FIFO设计，仅供参考-FIFO VHDL code
Date : 2025-12-21 Size : 394kb User : justin
[Embeded-SCM Develop] fifo DL : 0: fifo通用程序，可以作为模块化设计的通用程序-For fifo common procedures, modular design can be used as general-purpose program
Date : 2025-12-21 Size : 1kb User : 海阔天空
[Embeded-SCM Develop] BMI160 fifo DL : 0: 博士BMI160驱动代码，主要包括fifo的使用以及fifo数据获取和解码(Dr. BMI160 driver code, including the use of FIFO, as well as FIFO data acquisition and decoding)
Date : 2025-12-21 Size : 24kb User : 码农程序员

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