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[OS program] clk DL : 0: 现代电子系统课程设计基于DDS技术利用VHDL设计并制作一个数字式移相信号发生器。（1）基本要求： a．频率范围：1Hz～4kHz，频率步进为1Hz，输出频率可预置。 b．A、B两路正弦信号输出，10位输出数据宽度 c．相位差范围为0～359°，步进为1.4°，相位差值可预置。 d．数字显示预置的频率（10进制）、相位差值。（2）发挥部分 a．修改设计，增加幅度控制电路（如可以用一乘法器控制输出幅度）。 b．输出幅度峰峰值0.1～3.0V，步距0.1V，显示预置值。 -Modern electronic system design is based on DDS technology courses use VHDL to design and produce a digital shift Signal Generator. (1) the basic requirements: a. Frequency range: 1Hz ~ 4kHz, frequency step for the 1Hz, output frequency can be preset. b. A, B two sinusoidal signal output, 10-bit output data width c. Phase difference range of 0 ~ 359 °, stepping to 1.4 °, the phase difference value can be preset. d. Figures show that the frequency of Preferences (10 M), phase difference value. (2) to play a part of a. Modify the design to increase the rate of control circuit (for example, could use a multiplier to control the output rate). b. Peak-to-peak output rate of 0.1 ~ 3.0V, step 0.1V, show preset value.
Date : 2025-12-16 Size : 170kb User : 耳边
[OS program] Multiplier DL : 0: 基于VHDL语言，实现串并乘法器设计主程序-Based on the VHDL language, to achieve the main program string and Multiplier Design
Date : 2025-12-16 Size : 3kb User : 小涛