codestream design a module from a trip data flow c

Title: codestream

Category:
VHDL-FPGA-Verilog
Tags:
[Windows] [程序]
File Size:
8.68kb
Update:
2008-10-13
Downloads:
0 Times
Uploaded by:
xujia05

Description: design a module from a trip data flow channeling Lane detected bitstream "11100", this module includes reset, clk, datain and output pmatch

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