Description: The GRLIB IP Library is an integrated set of reusable IP cores, designed for system-on-chip (SOC) development. The IP cores are centered around the common on-chip bus, and use a coherent method for simulation and synthesis. The library is vendor independent, with support for different CAD tools and target technologies. A unique plugplay method is used to configure and connect the IP cores without the need to modify any global resources.
To Search:
File list (Check if you may need any files):
Download