Description: UART serial receiver module, through parameter, configuration parameters of the transmission rate, Data width and parity. Using Verilog. The user configured the parameters according to the serial port and configured FIFO according to the size of the buffer. The frame error (stop bit is not high), check errors, and read FIFO timeout (when FIFO is full,and new data come) and so on are examined.
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File list (Check if you may need any files):
BPS_CV_GEN.v
DIV16_CNT.v
PARITY_CHECK.v
RXD_SEEKER.v
START_BIT_CHECK.v
UART_USER_MOD.v
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