Description: Time Resolution for simulation is 1ps.
Waiting for 1 sub-compilation(s) to finish...
Compiled 4 Verilog Units
Built simulation executable G:/Techscope/On going Mtech/Miniproject/1DDWT/xilinx/top_dwt_isim_beh.exe
Fuse Memory Usage: 101756 KB
Fuse CPU Usage: 1435 ms
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idwt.vhd
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