Filename
Size
Date
add\add\add.done
 26 
 2012-03-12
add\add\add.eda.rpt
 2588 
 2012-03-12
add\add\add.flow.rpt
 6495 
 2012-03-12
add\add\add.map.rpt
 17789 
 2012-03-12
add\add\add.map.summary
 302 
 2012-03-12
add\add\add.qpf
 1268 
 2012-03-12
add\add\add.qsf
 3483 
 2017-10-26
add\add\add.v
 267 
 2012-03-12
add\add\add.v.bak
 248 
 2012-03-12
add\add\add_assignment_defaults.qdf
 48286 
 2017-09-26
add\add\add_nativelink_simulation.rpt
 988 
 2012-03-12
add\add\db\add.db_info
 153 
 2017-09-26
add\add\db\add.sld_design_entry.sci
 212 
 2017-10-26
add\add\db\logic_util_heursitic.dat
 0 
 2012-03-12
add\add\db\prev_cmp_add.qmsg
 3409 
 2012-03-12
add\add\incremental_db\README
 653 
 2012-03-12
add\add\incremental_db\compiled_partitions\add.db_info
 153 
 2017-09-26
add\add\incremental_db\compiled_partitions\add.root_partition.map.kpt
 497 
 2012-03-12
add\add\simulation\modelsim\add.vt
 2216 
 2012-03-12
add\add\simulation\modelsim\add.vt.bak
 3014 
 2012-03-12
add\add\simulation\modelsim\add_run_msim_rtl_verilog.do
 1466 
 2012-03-12
add\add\simulation\modelsim\add_run_msim_rtl_verilog.do.bak
 1466 
 2012-03-12
add\add\simulation\modelsim\msim_transcript
 12887 
 2012-03-12
add\add\simulation\modelsim\vsim.wlf
 73728 
 2012-03-12
add\add\simulation\modelsim\rtl_work\_info
 1724 
 2012-03-12
add\add\simulation\modelsim\rtl_work\_vmake
 26 
 2012-03-12
add\add\simulation\modelsim\rtl_work\@_opt\vopt22ajhw
 4320 
 2012-03-12
add\add\simulation\modelsim\rtl_work\@_opt\vopt2deniv
 3578 
 2012-03-12
add\add\simulation\modelsim\rtl_work\@_opt\vopt664ifv
 5204 
 2012-03-12
add\add\simulation\modelsim\rtl_work\@_opt\vopt6z0g2w
 14048 
 2012-03-12
add\add\simulation\modelsim\rtl_work\@_opt\vopt9rnczv
 354 
 2012-03-12
add\add\simulation\modelsim\rtl_work\@_opt\voptdyd9dv
 6277 
 2012-03-12
add\add\simulation\modelsim\rtl_work\@_opt\voptg7030w
 827 
 2012-03-12
add\add\simulation\modelsim\rtl_work\@_opt\voptgvn6yk
 12667 
 2012-03-12
add\add\simulation\modelsim\rtl_work\@_opt\voptkbc3yk
 1732 
 2012-03-12
add\add\simulation\modelsim\rtl_work\@_opt\voptkqm00w
 339 
 2012-03-12
add\add\simulation\modelsim\rtl_work\@_opt\voptq7bxzv
 452 
 2012-03-12
add\add\simulation\modelsim\rtl_work\@_opt\voptqq7tmw
 82 
 2012-03-12
add\add\simulation\modelsim\rtl_work\@_opt\voptv7xqmw
 1662 
 2012-03-12
add\add\simulation\modelsim\rtl_work\@_opt\voptvd1w7w
 7616 
 2012-03-12
add\add\simulation\modelsim\rtl_work\@_opt\voptvq0szv
 2567 
 2012-03-12
add\add\simulation\modelsim\rtl_work\@_opt\voptyqikmw
 629 
 2012-03-12
add\add\simulation\modelsim\rtl_work\@_opt\voptz8knkw
 700 
 2012-03-12
add\add\simulation\modelsim\rtl_work\@_opt\voptzjrsmv
 3128 
 2012-03-12
add\add\simulation\modelsim\rtl_work\@_opt\_deps
 2886 
 2012-03-12
add\add\simulation\modelsim\rtl_work\add\_primary.dat
 339 
 2012-03-12
add\add\simulation\modelsim\rtl_work\add\_primary.dbs
 827 
 2012-03-12
add\add\simulation\modelsim\rtl_work\add\_primary.vhd
 354 
 2012-03-12
add\add\simulation\modelsim\rtl_work\add_vlg_tst\_primary.dat
 629 
 2012-03-12
add\add\simulation\modelsim\rtl_work\add_vlg_tst\_primary.dbs
 1662 
 2012-03-12
add\add\simulation\modelsim\rtl_work\add_vlg_tst\_primary.vhd
 82 
 2012-03-12
add\add\simulation\modelsim\verilog_libs\altera_mf_ver\_info
 12667 
 2012-03-12
add\add\simulation\modelsim\verilog_libs\altera_mf_ver\_vmake
 26 
 2012-03-12
add\add\simulation\modelsim\verilog_libs\altera_mf_ver\@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s\_primary.dat
 25006 
 2012-03-12
add\add\simulation\modelsim\verilog_libs\altera_mf_ver\@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s\_primary.dbs
 79888 
 2012-03-12
add\add\simulation\modelsim\verilog_libs\altera_mf_ver\@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s\_primary.vhd
 104 
 2012-03-12
add\add\simulation\modelsim\verilog_libs\altera_mf_ver\@a@l@t@e@r@a_@m@f_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n\_primary.dat
 1808 
 2012-03-12
add\add\simulation\modelsim\verilog_libs\altera_mf_ver\@a@l@t@e@r@a_@m@f_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n\_primary.dbs
 5884 
 2012-03-12
add\add\simulation\modelsim\verilog_libs\altera_mf_ver\@a@l@t@e@r@a_@m@f_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n\_primary.vhd
 110 
 2012-03-12
add\add\simulation\modelsim\verilog_libs\altera_mf_ver\@a@l@t@e@r@a_@m@f_@m@e@m@o@r@y_@i@n@i@t@i@a@l@i@z@a@t@i@o@n\_primary.dat
 19024 
 2012-03-12
add\add\simulation\modelsim\verilog_libs\altera_mf_ver\@a@l@t@e@r@a_@m@f_@m@e@m@o@r@y_@i@n@i@t@i@a@l@i@z@a@t@i@o@n\_primary.dbs
 93842 
 2012-03-12
add\add\simulation\modelsim\verilog_libs\altera_mf_ver\@a@l@t@e@r@a_@m@f_@m@e@m@o@r@y_@i@n@i@t@i@a@l@i@z@a@t@i@o@n\_primary.vhd
 122 
 2012-03-12
add\add\simulation\modelsim\verilog_libs\altera_mf_ver\@m@f_cycloneiiigl_m_cntr\_primary.dat
 912 
 2012-03-12
add\add\simulation\modelsim\verilog_libs\altera_mf_ver\@m@f_cycloneiiigl_m_cntr\_primary.dbs
 3315 
 2012-03-12
add\add\simulation\modelsim\verilog_libs\altera_mf_ver\@m@f_cycloneiiigl_m_cntr\_primary.vhd
 438 
 2012-03-12
add\add\simulation\modelsim\verilog_libs\altera_mf_ver\@m@f_cycloneiiigl_n_cntr\_primary.dat
 719 
 2012-03-12
add\add\simulation\modelsim\verilog_libs\altera_mf_ver\@m@f_cycloneiiigl_n_cntr\_primary.dbs
 2669 
 2012-03-12
add\add\simulation\modelsim\verilog_libs\altera_mf_ver\@m@f_cycloneiiigl_n_cntr\_primary.vhd
 312 
 2012-03-12
add\add\simulation\modelsim\verilog_libs\altera_mf_ver\@m@f_cycloneiiigl_pll\_primary.dat
 69042 
 2012-03-12
add\add\simulation\modelsim\verilog_libs\altera_mf_ver\@m@f_cycloneiiigl_pll\_primary.dbs
 239614 
 2012-03-12
add\add\simulation\modelsim\verilog_libs\altera_mf_ver\@m@f_cycloneiiigl_pll\_primary.vhd
 19172 
 2012-03-12
add\add\simulation\modelsim\verilog_libs\altera_mf_ver\@m@f_cycloneiiigl_scale_cntr\_primary.dat
 1458 
 2012-03-12
add\add\simulation\modelsim\verilog_libs\altera_mf_ver\@m@f_cycloneiiigl_scale_cntr\_primary.dbs
 5092 
 2012-03-12
add\add\simulation\modelsim\verilog_libs\altera_mf_ver\@m@f_cycloneiiigl_scale_cntr\_primary.vhd
 572 
 2012-03-12
add\add\simulation\modelsim\verilog_libs\altera_mf_ver\@m@f_cycloneiii_pll\_primary.dat
 68098 
 2012-03-12
add\add\simulation\modelsim\verilog_libs\altera_mf_ver\@m@f_cycloneiii_pll\_primary.dbs
 228887 
 2012-03-12
add\add\simulation\modelsim\verilog_libs\altera_mf_ver\@m@f_cycloneiii_pll\_primary.vhd
 18892 
 2012-03-12
add\add\simulation\modelsim\verilog_libs\altera_mf_ver\@m@f_pll_reg\_primary.dat
 492 
 2012-03-12
add\add\simulation\modelsim\verilog_libs\altera_mf_ver\@m@f_pll_reg\_primary.dbs
 1316 
 2012-03-12
add\add\simulation\modelsim\verilog_libs\altera_mf_ver\@m@f_pll_reg\_primary.vhd
 354 
 2012-03-12
add\add\simulation\modelsim\verilog_libs\altera_mf_ver\@m@f_stratixiii_pll\_primary.dat
 84565 
 2012-03-12
add\add\simulation\modelsim\verilog_libs\altera_mf_ver\@m@f_stratixiii_pll\_primary.dbs
 289123 
 2012-03-12
add\add\simulation\modelsim\verilog_libs\altera_mf_ver\@m@f_stratixiii_pll\_primary.vhd
 29031 
 2012-03-12
add\add\simulation\modelsim\verilog_libs\altera_mf_ver\@m@f_stratixii_pll\_primary.dat
 73752 
 2012-03-12
add\add\simulation\modelsim\verilog_libs\altera_mf_ver\@m@f_stratixii_pll\_primary.dbs
 244823 
 2012-03-12
add\add\simulation\modelsim\verilog_libs\altera_mf_ver\@m@f_stratixii_pll\_primary.vhd
 18444 
 2012-03-12
add\add\simulation\modelsim\verilog_libs\altera_mf_ver\@m@f_stratix_pll\_primary.dat
 81056 
 2012-03-12
add\add\simulation\modelsim\verilog_libs\altera_mf_ver\@m@f_stratix_pll\_primary.dbs
 267356 
 2012-03-12
add\add\simulation\modelsim\verilog_libs\altera_mf_ver\@m@f_stratix_pll\_primary.vhd
 23619 
 2012-03-12
add\add\simulation\modelsim\verilog_libs\altera_mf_ver\alt3pram\_primary.dat
 10552 
 2012-03-12
add\add\simulation\modelsim\verilog_libs\altera_mf_ver\alt3pram\_primary.dbs
 28772 
 2012-03-12
add\add\simulation\modelsim\verilog_libs\altera_mf_ver\alt3pram\_primary.vhd
 3712 
 2012-03-12
add\add\simulation\modelsim\verilog_libs\altera_mf_ver\altaccumulate\_primary.dat
 3901 
 2012-03-12
add\add\simulation\modelsim\verilog_libs\altera_mf_ver\altaccumulate\_primary.dbs
 12383 
 2012-03-12
add\add\simulation\modelsim\verilog_libs\altera_mf_ver\altaccumulate\_primary.vhd
 1440 
 2012-03-12
add\add\simulation\modelsim\verilog_libs\altera_mf_ver\altclklock\_primary.dat
 14089 
 2012-03-12
add\add\simulation\modelsim\verilog_libs\altera_mf_ver\altclklock\_primary.dbs
 45973 
 2012-03-12
add\add\simulation\modelsim\verilog_libs\altera_mf_ver\altclklock\_primary.vhd
 3662 
 2012-03-12
add\add\simulation\modelsim\verilog_libs\altera_mf_ver\altddio_bidir\_primary.dat
 1861 
 2012-03-12
add\add\simulation\modelsim\verilog_libs\altera_mf_ver\altddio_bidir\_primary.dbs
 5227 
 2012-03-12