Description: A 32-bit parallel and highly pipelined Cyclic Redundancy Code (CRC) generator is presented. The design can handle 5 different channels at an input rate of 2Gbps each (the total output throughput is 5x4Gbps.)
The generated CRCs are compatible with the 32-bit Ethernet standards. The circuit has been implemented with standard cells in a 0.35Micron standard CMOS process using the properties of Galois Fields and has been conceived as a free IP.
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File list (Check if you may need any files):
CRC-generator\CRC-generator\CRC_report.ps
.............\.............\data\data_in.dat
.............\.............\....\data_input_in.dat
.............\.............\....\data_input_out.dat
.............\.............\....\data_multiplier_fcs_out.dat
.............\.............\....\data_multiplier_input.dat
.............\.............\....\data_multiplier_xor_out.dat
.............\.............\....\data_out.dat
.............\.............\....\data_xor_fcs.dat
.............\.............\....\data_xor_gf.dat
.............\.............\....\data_xor_input.dat
.............\.............\....\data_xor_out.dat
.............\.............\README
.............\.............\script
.............\.............\stop
.............\.............\.yn\.synopsys_dc.setup
.............\.............\...\.synopsys_vss.setup
.............\.............\...\CRC_top_syn.db
.............\.............\...\CRC_top_syn.v
.............\.............\vhdl\big_xor.vhd
.............\.............\....\big_xor_tb.vhd
.............\.............\....\crc_modif.vhd
.............\.............\....\CRC_top.vhd
.............\.............\....\CRC_top_syn.vhd
.............\.............\....\CRC_top_syn_tb.vhd
.............\.............\....\CRC_top_tb.vhd
.............\.............\....\CRC_top_tb.vhd~
.............\.............\....\CRC_top_tb_ceros.vhd
.............\.............\....\ff_reset.vhd
.............\.............\....\gf_multiplier.vhd
.............\.............\....\gf_multiplier.vhd~
.............\.............\....\gf_multiplier_tb.vhd
.............\.............\....\gf_registers.vhd
.............\.............\....\gf_registers.vhd~
.............\.............\....\gf_xor.vhd
.............\.............\....\input_registers.vhd
.............\.............\....\input_wait.vhd
.............\.............\....\input_wait_bak.vhd
.............\.............\....\input_wait_tb.vhd
.............\.............\WORK\.synopsys_dc.setup
.............\.............\....\.synopsys_vss.setup
.............\.............\....\sparcOS5
.............\.............\data
.............\.............\syn
.............\.............\vhdl
.............\.............\WORK
.............\CRC-generator
CRC-generator
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