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Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: Buf_FiFo Download
 Description: verilog write FIFO, inside the IP core and control module,
 Downloaders recently: [More information of uploader 王红伟]
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Buf_FiFo\Buf_fifo.v
........\Buf_fifo.v.bak
........\Buf_fifo_core.qip
........\Buf_fifo_core.v
........\Buf_fifo_core_inst.v
........\fifo_write_if.v
........\fifo_write_if.v.bak
........\greybox_tmp\cbx_args.txt
........\greybox_tmp
Buf_FiFo

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