Description: FPGA-based SDRAM serial experiments, verilog language written annex is to do the experiment works, even on the serial port, the data will have to go under, 9600 baud, one stop bit, SDRAM clock is 96MHz, automatically generated data FPGA the correct result is output to the FF 00 is incremented by one, recycle. The project is relatively small warning, a warning is intentionally basic timing also has converged.
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File list (Check if you may need any files):
SDRAM_96M\DATA_GEN.v
.........\db\altsyncram_a011.tdf
.........\..\alt_synch_pipe_b7d.tdf
.........\..\alt_synch_pipe_c7d.tdf
.........\..\alt_synch_pipe_d7d.tdf
.........\..\alt_synch_pipe_e7d.tdf
.........\..\alt_synch_pipe_f7d.tdf
.........\..\alt_synch_pipe_g7d.tdf
.........\..\a_gray2bin_6ib.tdf
.........\..\a_graycounter_3p6.tdf
.........\..\a_graycounter_v6c.tdf
.........\..\cmpr_n76.tdf
.........\..\dcfifo_2pf1.tdf
.........\..\dcfifo_lpf1.tdf
.........\..\dcfifo_tve1.tdf
.........\..\dffpipe_909.tdf
.........\..\dffpipe_a09.tdf
.........\..\dffpipe_b09.tdf
.........\..\dffpipe_c09.tdf
.........\..\dffpipe_d09.tdf
.........\..\dffpipe_e09.tdf
.........\..\dffpipe_f09.tdf
.........\..\logic_util_heursitic.dat
.........\..\PLL_CTL_altpll.v
.........\..\prev_cmp_SDRAM_TEST.qmsg
.........\..\SDRAM_TEST.amm.cdb
.........\..\SDRAM_TEST.asm.qmsg
.........\..\SDRAM_TEST.asm.rdb
.........\..\SDRAM_TEST.asm_labs.ddb
.........\..\SDRAM_TEST.cbx.xml
.........\..\SDRAM_TEST.cmp.bpm
.........\..\SDRAM_TEST.cmp.cdb
.........\..\SDRAM_TEST.cmp.hdb
.........\..\SDRAM_TEST.cmp.kpt
.........\..\SDRAM_TEST.cmp.logdb
.........\..\SDRAM_TEST.cmp.rdb
.........\..\SDRAM_TEST.cmp_merge.kpt
.........\..\SDRAM_TEST.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
.........\..\SDRAM_TEST.cycloneive_io_sim_cache.45um_ss_1200mv_0c_slow.hsd
.........\..\SDRAM_TEST.cycloneive_io_sim_cache.45um_ss_1200mv_85c_slow.hsd
.........\..\SDRAM_TEST.db_info
.........\..\SDRAM_TEST.fit.qmsg
.........\..\SDRAM_TEST.hier_info
.........\..\SDRAM_TEST.hif
.........\..\SDRAM_TEST.idb.cdb
.........\..\SDRAM_TEST.lpc.html
.........\..\SDRAM_TEST.lpc.rdb
.........\..\SDRAM_TEST.lpc.txt
.........\..\SDRAM_TEST.map.bpm
.........\..\SDRAM_TEST.map.cdb
.........\..\SDRAM_TEST.map.hdb
.........\..\SDRAM_TEST.map.kpt
.........\..\SDRAM_TEST.map.logdb
.........\..\SDRAM_TEST.map.qmsg
.........\..\SDRAM_TEST.map_bb.cdb
.........\..\SDRAM_TEST.map_bb.hdb
.........\..\SDRAM_TEST.map_bb.logdb
.........\..\SDRAM_TEST.pre_map.cdb
.........\..\SDRAM_TEST.pre_map.hdb
.........\..\SDRAM_TEST.root_partition.map.reg_db.cdb
.........\..\SDRAM_TEST.rpp.qmsg
.........\..\SDRAM_TEST.rtlv.hdb
.........\..\SDRAM_TEST.rtlv_sg.cdb
.........\..\SDRAM_TEST.rtlv_sg_swap.cdb
.........\..\SDRAM_TEST.sgate.rvd
.........\..\SDRAM_TEST.sgate_sm.rvd
.........\..\SDRAM_TEST.sgdiff.cdb
.........\..\SDRAM_TEST.sgdiff.hdb
.........\..\SDRAM_TEST.sld_design_entry.sci
.........\..\SDRAM_TEST.sld_design_entry_dsc.sci
.........\..\SDRAM_TEST.smart_action.txt
.........\..\SDRAM_TEST.sta.qmsg
.........\..\SDRAM_TEST.sta.rdb
.........\..\SDRAM_TEST.sta_cmp.8_slow_1200mv_85c.tdb
.........\..\SDRAM_TEST.syn_hier_info
.........\..\SDRAM_TEST.taw.rdb
.........\..\SDRAM_TEST.tiscmp.fastest_slow_1200mv_0c.ddb
.........\..\SDRAM_TEST.tiscmp.fastest_slow_1200mv_85c.ddb
.........\..\SDRAM_TEST.tiscmp.fast_1200mv_0c.ddb
.........\..\SDRAM_TEST.tiscmp.slow_1200mv_0c.ddb
.........\..\SDRAM_TEST.tiscmp.slow_1200mv_85c.ddb
.........\..\SDRAM_TEST.tis_db_list.ddb
.........\..\SDRAM_TEST.tmw_info
.........\greybox_tmp\cbx_args.txt
.........\incremental_db\compiled_partitions\SDRAM_TEST.db_info
.........\..............\...................\SDRAM_TEST.root_partition.cmp.cdb
.........\..............\...................\SDRAM_TEST.root_partition.cmp.dfp
.........\..............\...................\SDRAM_TEST.root_partition.cmp.hdb
.........\..............\...................\SDRAM_TEST.root_partition.cmp.kpt
.........\..............\...................\SDRAM_TEST.root_partition.cmp.logdb
.........\..............\...................\SDRAM_TEST.root_partition.cmp.rcfdb
.........\..............\...................\SDRAM_TEST.root_partition.map.cdb
.........\..............\...................\SDRAM_TEST.root_partition.map.dpi
.........\..............\...................\SDRAM_TEST.root_partition.map.hbdb.cdb
.........\..............\...................\SDRAM_TEST.root_partition.map.hbdb.hb_info
.........\..............\...................\SDRAM_TEST.root_partition.map.hbdb.hdb
.........\..............\...................\SDRAM
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