Welcome![Sign In][Sign Up]
Location:
Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: stopwatch Download
 Description: A stopwatch circuit that counts minutes and seconds, and has reset, pause functionalities. Designed using Verilog.
 Downloaders recently: [More information of uploader bologna]
 To Search:
File list (Check if you may need any files):
 

iseconfig
.........\clock.xreport
.........\lab3.projectmgr
_xmsgs
clock.v
controller.v
counter_min.v
counter_sec.v
display.v
extract_digits.v
fuse.xmsgs
fuseRelaunch.cmd
lab3.gise
lab3.xise
tb_clock.v
tb_counter_min.v
tb_counter_sec.v
tb_counter_sec_isim_beh1.wdb
tb_display.v
tb_extract_digits.v
    

CodeBus www.codebus.net