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SRAM期刊论文\2010期刊\A 0.45-V 300-MHz 10T Flowthrough SRAM With Expanded WRITEREAD Stability and Speed-Area-Wise Array for Sub-0.5-V Chips.pdf
............\........\A Differential Data-Aware Power-Supplied (D__AP) 8T SRAM CellWith Expanded WriteRead Stabilities for Lower VDDmin Applications.pdf
............\........\A Low-Power SRAM Using Bit-Line Charge-Recycling for Read and Write Operations.pdf
............\...1期刊\A Novel Column-Decoupled 8T Cell for Low-Power Differential and Domino-Based SRAM Design.pdf
............\........\Design and Sensitivity Analysis of a New Current-Mode Sense Amplifier for Low-Power SRAM.pdf
............\........\Impacts of NBTIPBTI and Contact Resistance on Power-Gated SRAM With High-Metal-Gate Devices.pdf
............\........\Impacts of NBTIPBTI on Timing Control Circuits and Degradation Tolerant Design in Nanoscale CMOS SRAM.pdf
............\........\SRAM Write-Ability Improvement With Transient Negative Bit-Line Voltage.pdf
............\...2期刊\A 40-nm Sub-Threshold 5T SRAM Bit Cell With Improved Read and Write Stability.pdf
............\........\Compact Measurement Schemes for Bit-Line Swing
 Sense Amplifier Offset Voltage
 and Word-Line Pulse Width to Characterize Sensing Tolerance Margin in a 40 nm Fully Functional Embedded SRAM.pdf
............\........\Enhancing NBTI Recovery in SRAM Arrays Through Recovery Boosting.pdf
............\........\Near Threshold Voltage Word-Line Voltage Injection Self-Convergence Scheme for Local Electron Injected Asymmetric Pass Gate Transistor 6T-SRAM.pdf
............\........\Nonrandom Device Mismatch Considerations in Nanoscale SRAM.pdf
............\...3期刊\A 6T-SRAM With a Post-Process Electron Injection Scheme That Pinpoints and Simultaneously Repairs Disturb Fails.pdf
............\........\A Sub-0.3 V Area-Efficient L-Shaped 7T SRAM With Read Bitline Swing Expansion Schemes Based on Boosted Read-Bitline Asymmetric-V.pdf
............\........\An Efficient Optimization Based Method to Evaluate the DRV of SRAM Cells.pdf
............\........\Highly Energy-Efficient SRAM With Hierarchical Bit Line Charge-Sharing Method Using Non-Selected Bit Line Charges.pdf
............\........\In Situ SRAM Static Stability Estimation in 65nm CMOS.pdf
............\...4期刊\40 nm Bit-Interleaving 12T Subthreshold SRAM With Data-Aware Write-Assist.pdf
............\........\A Comprehensive Comparison of Data Stability Enhancement Techniques With Novel Nanoscale SRAM Cells Under Parameter Fluctuations.pdf
............\........\Application-Specific SRAM Design Using Output Prediction to Reduce Bit-Line Switching Activity and Statistically Gated Sense Amplifiers.pdf
............\........\Average-8T Differential-Sensing Subthreshold SRAM With Bit Interleaving and 1k Bits Per Bitline.pdf
............\........\Increase in Read Noise Margin of Single-Bit-Line SRAM Using Adiabatic Change of Word Line Voltage.pdf
............\........\Scalable 0.35 V to 1.2 V SRAM Bitcell Design From 65 nm CMOS to 28 nm FDSOI.pdf
............\........\Stability Estimation of a 6T-SRAM Cell Using a Nonlinear Regression.pdf
............\........\Sub-threshold SRAM bit cell pnn for VDDmin and power reduction.pdf
............\2010期刊
............\2011期刊
............\2012期刊
............\2013期刊
............\2014期刊
SRAM期刊论文