Description: 1. Customize a dual-port RAM, DualPortRAM
2. In the top-level project instantiate RAM
3. To achieve this project, do gate-level simulator in Quartus II Simulation
In this works in ModelSim RTL-level simulation
To Search:
File list (Check if you may need any files):
Example-b4-1\Project\db\TOP.db_info
............\.......\..\TOP.eco.cdb
............\.......\..\TOP.sld_design_entry.sci
............\.......\Simulation\altera_mf.v
............\.......\..........\sim.do
............\.......\..........\wave.do
............\.......\TOP.qpf
............\.......\TOP.qsf
............\.......\TOP.qws
............\.......\TOP_assignment_defaults.qdf
............\Solution\db\TOP.db_info
............\........\..\TOP.eco.cdb
............\........\..\TOP.sld_design_entry.sci
............\........\DualPortRAM.bsf
............\........\DualPortRAM.v
............\........\Simulation\altera_mf.v
............\........\..........\DualPortRAM.v
............\........\..........\sim.do
............\........\..........\TOP.v
............\........\..........\TOP.vt
............\........\..........\wave.do
............\........\TOP.bdf
............\........\TOP.qpf
............\........\TOP.qsf
............\........\TOP.qws
............\........\TOP.v
............\........\TOP.vt
............\........\TOP.vwf
............\........\TOP_assignment_defaults.qdf
............\示例说明.doc
............\Project\db
............\.......\Simulation
............\Solution\db
............\........\Simulation
............\Project
............\Solution
Example-b4-1
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