Description: shift register 7495 four d flip flop 5 mux
5495A/DM7495
4-Bit Parallel Access Shift Registers
General Description
These 4-bit registers feature parallel and serial inputs, parallel
outputs, mode control, and two clock inputs. The registers
have three modes of operation.
Parallel (broadside) load
Shift right (the direction QA toward QD)
Shift left (the direction QD toward QA)
Parallel loading is accomplished by applying the four bits of
data and taking the mode control input high. The data is
loaded into the associated flip-flops and appears at the outputs
after the high-to-low transition of the clock-2 input. During
loading, the entry of serial data is inhibited.
Shift right is accomplished on the high-to-low transition of
clock 1 when the mode control is low shift left is accomplished
on the high-to-low transition of clock 2 when th
To Search:
File list (Check if you may need any files):
7495\.lso
....\7495.ise
....\7495.ise_ISE_Backup
....\7495.restore
....\dff.vhd
....\isim\work\dff\behavioral.h
....\....\....\...\mingw\behavioral.obj
....\....\....\hdllib.ref
....\....\....\hdpdeps.ref
....\....\....\mux\behavioral.h
....\....\....\...\mingw\behavioral.obj
....\....\....\shift_reg\behavioral.h
....\....\....\.........\mingw\behavioral.obj
....\....\....\.ub00\vhpl00.vho
....\....\....\.....\vhpl01.vho
....\....\....\.....\vhpl02.vho
....\....\....\.....\vhpl03.vho
....\....\....\.....\vhpl04.vho
....\....\....\.....\vhpl05.vho
....\....\....\.....\vhpl06.vho
....\....\....\.....\vhpl07.vho
....\....\....\test\mingw\testbench_arch.obj
....\....\....\....\testbench_arch.h
....\....\....\....\xsimtestbench_arch.cpp
....\isim.cmd
....\isim.hdlsourcefiles
....\isim.log
....\.....tmp_save\_1
....\isimwavedata.xwv
....\mux.vhd
....\pepExtractor.prj
....\results.txt
....\shift_reg.prj
....\shift_reg.stx
....\shift_reg.vhd
....\shift_reg.xst
....\shift_reg_summary.html
....\shift_reg_vhdl.prj
....\simulate_dofile.log
....\simulate_dofile.log_back
....\test.ant
....\test.jhd
....\test.tbw
....\test.vhw
....\test.xwv
....\test.xwv_bak
....\test_beh.prj
....\test_bencher.prj
....\test_isim_beh.exe
....\test_isim_beh.wfs
....\xilinxsim.ini
....\.st\work\hdllib.ref
....\...\....\hdpdeps.ref
....\...\....\sub00\vhpl00.vho
....\...\....\.....\vhpl01.vho
....\...\....\.....\vhpl02.vho
....\...\....\.....\vhpl03.vho
....\...\....\.....\vhpl04.vho
....\...\....\.....\vhpl05.vho
....\_xmsgs\fuse.xmsgs
....\......\vhpcomp.xmsgs
....\......\xst.xmsgs
....\__ISE_repository_7495.ise_.lock
....\isim\work\dff\mingw
....\....\....\mux\mingw
....\....\....\shift_reg\mingw
....\....\....\test\mingw
....\....\....\dff
....\....\....\mux
....\....\....\shift_reg
....\....\....\sub00
....\....\....\test
....\xst\work\sub00
....\isim\file graph
....\....\work
....\xst\file graph
....\...\projnav.tmp
....\...\work
....\isim
....\isim.tmp_save
....\xst
....\_xmsgs
7495
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