Description: SPI Master Core
HDL: VHDL 93
Compatibility: all FPGAs, CPLDs
parameterization:
- variable data width
- Phase/polarity configurable
- selectable buffer depth
- serial clock devision due to system clock
package usage:
IEEE.STD_LOGIC_1164
IEEE.NUMERIC_STD
work.general_signal_processing_pkg (included)
Testbench for simulation included.
Core Tested on Lattice XP2 CPLD Brevia development kit and FPGAs Xilinx Spartan-3E and Altera Cyclone-4E (industrial application)
To Search:
File list (Check if you may need any files):
SPI Core_nguyen\general_signal_processing_pkg.vhd
...............\readme.txt
...............\spi_master_rev.vhd
...............\spi_master_rev_TB.vhd
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