Title:
Low-Error-and-Hardware-Efficient-Fixed-Width-Mult
Download
Description: VERILOG Code for IEEE Paper Low-Error and Hardware-Efficient Fixed-Width Multiplier
by Using the Dual-Group Minor Input Correction Vector
to Lower Input Correction Vector Compensation Error
Run by ModelSim 6.2 software
Here paper output and modified paper output can be provided.
Phase-1 folder consists of paper output High speed msb multiplication. In phase-2 folder consists of slight change before the multiplication process check the if the multiplication result will give msb or not , if it s possible continue multiplication process otherwise zero can be put on the result.
To Search:
File list (Check if you may need any files):
Low-Error and Hardware-Efficient Fixed-Width Multiplier\06035756.pdf
.......................................................\output.docx
.......................................................\Phase-1\Soft\demorgan_mul.v
.......................................................\.......\....\demorgan_mul.v.bak
.......................................................\.......\....\demorgan_sim.v
.......................................................\.......\....\demorgan_sim.v.bak
.......................................................\.......\....\full_adder.v
.......................................................\.......\....\half_adder.v
.......................................................\.......\....\modelsim.ini
.......................................................\.......\....\multiplier.v
.......................................................\.......\....\multiplier.v.bak
.......................................................\.......\....\pp_gen.v
.......................................................\.......\....\pp_gen.v.bak
.......................................................\.......\....\vsim.wlf
.......................................................\.......\....\work\demorgan_mul\verilog.asm
.......................................................\.......\....\....\............\_primary.dat
.......................................................\.......\....\....\............\_primary.vhd
.......................................................\.......\....\....\demorgan_mul
.......................................................\.......\....\....\.........sim\verilog.asm
.......................................................\.......\....\....\............\_primary.dat
.......................................................\.......\....\....\............\_primary.vhd
.......................................................\.......\....\....\demorgan_sim
.......................................................\.......\....\....\full_adder\verilog.asm
.......................................................\.......\....\....\..........\_primary.dat
.......................................................\.......\....\....\..........\_primary.vhd
.......................................................\.......\....\....\full_adder
.......................................................\.......\....\....\half_adder\verilog.asm
.......................................................\.......\....\....\..........\_primary.dat
.......................................................\.......\....\....\..........\_primary.vhd
.......................................................\.......\....\....\half_adder
.......................................................\.......\....\....\multiplier\verilog.asm
.......................................................\.......\....\....\..........\_primary.dat
.......................................................\.......\....\....\..........\_primary.vhd
.......................................................\.......\....\....\multiplier
.......................................................\.......\....\....\pp_gen\verilog.asm
.......................................................\.......\....\....\......\_primary.dat
.......................................................\.......\....\....\......\_primary.vhd
.......................................................\.......\....\....\pp_gen
.......................................................\.......\....\....\test\verilog.asm
.......................................................\.......\....\....\....\_primary.dat
.......................................................\.......\....\....\....\_primary.vhd
.......................................................\.......\....\....\test
.......................................................\.......\....\....\_info
.......................................................\.......\....\....\_temp
.......................................................\.......\....\work
.......................................................\.......\Soft
..................................
