my_first_fpga\Block.bdf
.............\counter_bus_mux.bsf
.............\counter_bus_mux.qip
.............\counter_bus_mux.v
.............\counter_bus_mux_bb.v
.............\db\logic_util_heursitic.dat
.............\..\mux_arc.tdf
.............\..\my_first_fpga.ae.hdb
.............\..\my_first_fpga.amm.cdb
.............\..\my_first_fpga.asm.qmsg
.............\..\my_first_fpga.asm.rdb
.............\..\my_first_fpga.asm_labs.ddb
.............\..\my_first_fpga.cbx.xml
.............\..\my_first_fpga.cmp.bpm
.............\..\my_first_fpga.cmp.cdb
.............\..\my_first_fpga.cmp.hdb
.............\..\my_first_fpga.cmp.kpt
.............\..\my_first_fpga.cmp.logdb
.............\..\my_first_fpga.cmp.rdb
.............\..\my_first_fpga.cmp_merge.kpt
.............\..\my_first_fpga.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
.............\..\my_first_fpga.cycloneive_io_sim_cache.45um_ss_1200mv_0c_slow.hsd
.............\..\my_first_fpga.cycloneive_io_sim_cache.45um_ss_1200mv_85c_slow.hsd
.............\..\my_first_fpga.db_info
.............\..\my_first_fpga.fit.qmsg
.............\..\my_first_fpga.hier_info
.............\..\my_first_fpga.hif
.............\..\my_first_fpga.idb.cdb
.............\..\my_first_fpga.lpc.html
.............\..\my_first_fpga.lpc.rdb
.............\..\my_first_fpga.lpc.txt
.............\..\my_first_fpga.map.bpm
.............\..\my_first_fpga.map.cdb
.............\..\my_first_fpga.map.hdb
.............\..\my_first_fpga.map.kpt
.............\..\my_first_fpga.map.logdb
.............\..\my_first_fpga.map.qmsg
.............\..\my_first_fpga.map_bb.cdb
.............\..\my_first_fpga.map_bb.hdb
.............\..\my_first_fpga.map_bb.logdb
.............\..\my_first_fpga.pre_map.cdb
.............\..\my_first_fpga.pre_map.hdb
.............\..\my_first_fpga.rtlv.hdb
.............\..\my_first_fpga.rtlv_sg.cdb
.............\..\my_first_fpga.rtlv_sg_swap.cdb
.............\..\my_first_fpga.sgdiff.cdb
.............\..\my_first_fpga.sgdiff.hdb
.............\..\my_first_fpga.sld_design_entry.sci
.............\..\my_first_fpga.sld_design_entry_dsc.sci
.............\..\my_first_fpga.smart_action.txt
.............\..\my_first_fpga.sta.qmsg
.............\..\my_first_fpga.sta.rdb
.............\..\my_first_fpga.sta_cmp.8_slow_1200mv_85c.tdb
.............\..\my_first_fpga.syn_hier_info
.............\..\my_first_fpga.tiscmp.fastest_slow_1200mv_0c.ddb
.............\..\my_first_fpga.tiscmp.fastest_slow_1200mv_85c.ddb
.............\..\my_first_fpga.tiscmp.fast_1200mv_0c.ddb
.............\..\my_first_fpga.tiscmp.slow_1200mv_0c.ddb
.............\..\my_first_fpga.tiscmp.slow_1200mv_85c.ddb
.............\..\my_first_fpga.tis_db_list.ddb
.............\..\pll_altpll.v
.............\..\prev_cmp_my_first_fpga.qmsg
.............\greybox_tmp\cbx_args.txt
.............\incremental_db\compiled_partitions\my_first_fpga.db_info
.............\..............\...................\my_first_fpga.root_partition.cmp.cdb
.............\..............\...................\my_first_fpga.root_partition.cmp.dfp
.............\..............\...................\my_first_fpga.root_partition.cmp.hdb
.............\..............\...................\my_first_fpga.root_partition.cmp.kpt
.............\..............\...................\my_first_fpga.root_partition.cmp.logdb
.............\..............\...................\my_first_fpga.root_partition.cmp.rcfdb
.............\..............\...................\my_first_fpga.root_partition.map.cdb
.............\..............\...................\my_first_fpga.root_partition.map.dpi
.............\..............\...................\my_first_fpga.root_partition.map.hbdb.cdb
.............\..............\...................\my_first_fpga.root_partition.map.hbdb.hb_info
.............\..............\...................\my_first_fpga.root_partition.map.hbdb.hdb
.............\..............\...................\my_first_fpga.root_partition.map.hbdb.sig
.............\..............\...................\my_first_fpga.root_partition.map.hdb
.............\..............\...................\my_first_fpga.root_partition.map.kpt
.........