xcv verilog prepared by the state machine detected

Title: xcv

Category:
VHDL-FPGA-Verilog
Tags:
[ASM] [源码]
File Size:
6.68kb
Update:
2008-10-13
Downloads:
0 Times
Uploaded by:
lulei30

Description: verilog prepared by the state machine detected 00,100 sequences. Achieve input : ... ... 011000010010000 output : 000000000100100 ... ... and test module used to verify the state is working

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