Description: FPGA on the use the verilog HDL implementation of the DDR controller, easy to understand, suitable for novice reference
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ddr_kongzhiqi\source\ddr_ctrl.v
.............\......\ddr_data.v
.............\......\ddr_par.v
.............\......\ddr_pll_orca.v
.............\......\ddr_pll_orca_sp.v
.............\......\ddr_sig.v
.............\......\ddr_top.v
.............\testbench\ddr_tb.v
.............\.........\stimulus.v
.............\source
.............\testbench
ddr_kongzhiqi
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