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Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: Latch Download
 Description: Latch on behalf of the FPGA using verilog HDL
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Latch\del_bak_work.bat
.....\Latch.v
.....\run_test_Wrap_Latch.do
.....\test_Wrap_Latch.tf
.....\wave_test_Wrap_Latch.do
.....\Wrap_Latch.v
Latch
    

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