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Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: part1 Download
 Description: a 4-bit synchronous counter using T-Flip Flops and AND gates in verilog code. Implements on educational kit Altera MAX7000s EPM7128SLC84-7.
 Downloaders recently: [More information of uploader Henna Tan]
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part1\cmp_state.ini
.....\db
.....\..\lab3_part1.asm.qmsg
.....\..\lab3_part1.cmp.cdb
.....\..\lab3_part1.cmp.ddb
.....\..\lab3_part1.cmp.hdb
.....\..\lab3_part1.cmp.rdb
.....\..\lab3_part1.cmp.tdb
.....\..\lab3_part1.csf.qmsg
.....\..\lab3_part1.db_info
.....\..\lab3_part1.fit.qmsg
.....\..\lab3_part1.frm.hdb
.....\..\lab3_part1.fsf.qmsg
.....\..\lab3_part1.hif
.....\..\lab3_part1.lab3_part1.sld_design_entry.sci
.....\..\lab3_part1.map.cdb
.....\..\lab3_part1.map.hdb
.....\..\lab3_part1.map.qmsg
.....\..\lab3_part1.pre_map.hdb
.....\..\lab3_part1.project.hdb
.....\..\lab3_part1.rtlv.hdb
.....\..\lab3_part1.rtlv_sg.cdb
.....\..\lab3_part1.rtlv_sg_swap.cdb
.....\..\lab3_part1.sgdiff.cdb
.....\..\lab3_part1.sgdiff.hdb
.....\..\lab3_part1.sim.hdb
.....\..\lab3_part1.sim.qmsg
.....\..\lab3_part1.sim.rdb
.....\..\lab3_part1.tan.qmsg
.....\..\lab3_part1_cmp.qrpt
.....\..\lab3_part1_hier_info
.....\..\lab3_part1_sim.qrpt
.....\..\lab3_part1_syn_hier_info
.....\..\lab3_part1-sim.vwf
.....\lab3_part1.asm.rpt
.....\lab3_part1.cdf
.....\lab3_part1.done
.....\lab3_part1.fit.eqn
.....\lab3_part1.fit.rpt
.....\lab3_part1.flow.rpt
.....\lab3_part1.map.eqn
.....\lab3_part1.map.rpt
.....\lab3_part1.pin
.....\lab3_part1.pof
.....\lab3_part1.qpf
.....\lab3_part1.qsf
.....\lab3_part1.qws
.....\lab3_part1.sim.rpt
.....\lab3_part1.tan.rpt
.....\lab3_part1.tan.summary
.....\lab3_part1.v
.....\lab3_part1.vwf
.....\seg_digit.v
.....\seg_ten.v
.....\sim.cfg
.....\tff0.v
    

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