sdr_ctrl\trunk\doc\sdram_controller_specs.pdf
........\.....\rtl\core\sdrc_bank_ctl.v
........\.....\...\....\sdrc_bank_fsm.v
........\.....\...\....\sdrc_bs_convert.v
........\.....\...\....\sdrc_core.v
........\.....\...\....\sdrc_define.v
........\.....\...\....\sdrc_req_gen.v
........\.....\...\....\sdrc_xfr_ctl.v
........\.....\...\filelist_rtl.f
........\.....\...\lib\async_fifo.v
........\.....\...\...\sync_fifo.v
........\.....\...\top\sdrc_top.v
........\.....\...\wb2sdrc\wb2sdrc.v
........\.....\synth\constraints\sdrc_synth.sdc
........\.....\.....\...........\sdrc_top.sdc
........\.....\verif\dump\Application-ReadRequest.jpg
........\.....\.....\....\Application-WriteRequest.jpg
........\.....\.....\....\SDR-16Bit-Read-Transaction.jpg
........\.....\.....\....\SDR-16Bit-Write-Transaction.jpg
........\.....\.....\....\SDR-32Bit-Read-Transaction.jpg
........\.....\.....\....\SDR-32Bit-Write-Transaction.jpg
........\.....\.....\log\core_sdr16_sim.log
........\.....\.....\...\core_sdr32_sim.log
........\.....\.....\...\core_sdr8_sim.log
........\.....\.....\...\core_SDR_16BIT_basic_test1.log
........\.....\.....\...\core_SDR_16BIT_complie.log
........\.....\.....\...\core_SDR_32BIT_basic_test1.log
........\.....\.....\...\core_SDR_32BIT_complie.log
........\.....\.....\...\core_SDR_8BIT_basic_test1.log
........\.....\.....\...\core_SDR_8BIT_complie.log
........\.....\.....\...\top_sdr16_sim.log
........\.....\.....\...\top_sdr32_sim.log
........\.....\.....\...\top_sdr8_sim.log
........\.....\.....\...\top_SDR_16BIT_basic_test1.log
........\.....\.....\...\top_SDR_16BIT_complie.log
........\.....\.....\...\top_SDR_32BIT_basic_test1.log
........\.....\.....\...\top_SDR_32BIT_complie.log
........\.....\.....\...\top_SDR_8BIT_basic_test1.log
........\.....\.....\...\top_SDR_8BIT_complie.log
........\.....\.....\model\IS42VM16400K.V
........\.....\.....\.....\mt48lc2m32b2.v
........\.....\.....\.....\mt48lc4m16.v
........\.....\.....\.....\mt48lc4m32b2.v
........\.....\.....\.....\mt48lc8m16a2.v
........\.....\.....\.....\mt48lc8m8a2.v
........\.....\.....\run\compile.modelsim
........\.....\.....\...\filelist.f
........\.....\.....\...\filelist_core.f
........\.....\.....\...\filelist_rtl.f
........\.....\.....\...\filelist_top.f
........\.....\.....\...\read.me
........\.....\.....\...\regression_analysis
........\.....\.....\...\run.do
........\.....\.....\...\run_all
........\.....\.....\...\run_modelsim
........\.....\.....\tb\tb_core.sv
........\.....\.....\..\tb_top.sv
........\.....\rtl\core
........\.....\...\defs
........\.....\...\lib
........\.....\...\top
........\.....\...\wb2sdrc
........\.....\synth\constraints
........\.....\verif\agents
........\.....\.....\defs
........\.....\.....\dump
........\.....\.....\lib
........\.....\.....\log
........\.....\.....\model
........\.....\.....\run
........\.....\.....\tb
........\.....\.....\test_case
........\.....\doc
........\.....\env
........\.....\models
........\.....\rtl
........\.....\synth
........\.....\verif
........\branches
........\tags
........\trunk
sdr_ctrl